- •Contents
- •List of Tables
- •List of Figures
- •Preface
- •About this document
- •Feedback
- •Introduction
- •1.1 About the ARM PrimeCell MultiPort Memory Controller (PL172)
- •1.2 Supported dynamic memory devices
- •1.3 Supported static memory devices
- •Functional Overview
- •2.1 PrimeCell MPMC functional description
- •2.2 Overview of a PrimeCell MPMC, ASIC, or ASSP system
- •2.3 Low power operation
- •2.4 Lock and semaphores
- •2.5 Arbitration
- •2.6 Memory bank select
- •2.7 Memory map
- •Programmer’s Model
- •3.1 About the programmer’s model
- •3.2 Register descriptions
- •Programmer’s Model for Test
- •4.1 PrimeCell MPMC test harness overview
- •4.2 Scan testing
- •4.3 Test registers
- •Static Memory Controller
- •5.1 Static memory device selection
- •5.2 Write-protection
- •5.3 Extended wait transfers
- •5.4 Memory mapped peripherals
- •5.5 Static memory initialization
- •5.6 Byte lane control
- •5.7 Byte lane control and databus steering for little and big-endian configurations
- •Dynamic Memory Controller
- •6.1 Write-protection
- •6.2 Access sequencing and memory width
- •6.3 Address mapping
- •6.4 Dynamic memory controller command descriptions
- •6.5 Generic SDRAM initialization example
- •6.6 Micron MT48LC4M16A2 SDRAM initialization example
- •6.8 Micron MT28F4M16S2 SyncFlash initialization example
- •6.9 Micron SyncFlash commands
- •Common Memory Transactions
- •7.1 Static and dynamic memory transaction latency
- •Test Interface Controller
- •8.1 About TIC
- •8.2 Sequence of events leading to entry into TIC test mode
- •System Connectivity
- •9.2 Self-refresh entry
- •9.3 Example system
- •Off-chip Connectivity
- •10.2 Pin count reduction by reducing databus width
- •10.3 Pin count reduction by removing functionality
- •10.4 Address pin reduction
- •10.5 Chip select pin reduction
- •10.6 Device support
- •10.7 Multiplexing static and dynamic memory pins
- •10.8 Reducing pin count by multiplexing MPMC pins
- •10.9 About MPMC timing
- •10.10 On-chip timing path
- •10.11 Off-chip timing path
- •10.12 Clock strategy
- •10.13 Clock ratios
- •10.14 Memory clock and fed-back clock strategy
- •Pad Interface Timing
- •A.1 Overview
- •A.2 Signal delay
- •A.3 Method to reduce delay
- •A.4 Methods to reduce skew
- •A.5 Methods to minimize the effects of delay and skew
- •A.6 Example SDRAM memory timing diagram
- •A.7 SDRAM memory timing paths
- •Troubleshooting
- •B.1 Troubleshooting
- •C.1 AHB register signals
- •C.2 AHB memory signals
- •C.3 Miscellaneous and clock signals
- •C.4 Pad interface and control signals
- •C.5 Test Interface Controller (TIC) signals
- •C.6 Scan test signals
Introduction
1.3Supported static memory devices
This section provides examples of static memory devices that are supported by the PrimeCell MPMC:
•ROM devices
•Page mode ROM devices
•SRAM devices
•Flash devices
•Page mode Flash devices.
Note
This is not an exhaustive list of supported devices.
1.3.1ROM devices
The PrimeCell MPMC supports the 128Mb Samsung K3N9V100M-YC.
1.3.2Page mode ROM devices
The PrimeCell MPMC supports the 128Mb Samsung K3P9V100M-YC.
1.3.3SRAM devices
The PrimeCell MPMC supports the following devices:
•256Kb IDT IDT 71V256SA20Y
•256Kb Micron MT28F004b5-672
•1Mb Micron MTSC2568-12
•4Mb Samsung K6F8016R6M
•4Mb Samsung K6R4016CK-12
•8Mb Samsung K6T8016C3M-70
•8Mb Samsung K6F8008R2M.
1.3.4Flash devices
The PrimeCell MPMC supports the 4Mb Micron MT28F004B5.
1.3.5Page mode Flash devices
The PrimeCell MPMC supports the 8Mb Intel 28F800F3 and the 4Mb Intel
E28F320J3A110.
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Copyright © 2002 ARM Limited. All rights reserved. |
ARM DDI 0215A |
Introduction
1.3.6Supported NAND flash memory devices
The PrimeCell MPMC supports the following devices by software:
•2Mb Samsung K9K2GO8Q0M
•4Mb Samsung K9F4008W0A.
ARM DDI 0215A |
Copyright © 2002 ARM Limited. All rights reserved. |
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Introduction
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Copyright © 2002 ARM Limited. All rights reserved. |
ARM DDI 0215A |