Appendix A

Pad Interface Timing

This appendix describes the signals that interface with the ARM PrimeCell MPMC block. It contains the following sections:

•Overview on page A-2

•Signal delay on page A-3

•Method to reduce delay on page A-4

•Methods to reduce skew on page A-6

•Methods to minimize the effects of delay and skew on page A-7

•Example SDRAM memory timing diagram on page A-8

•SDRAM memory timing paths on page A-9.

Pad Interface Timing

A.1 Overview

The performance of the PrimeCell MPMC is normally limited by the speed that data, address, and control information can be sent to, and data can be read from, the SDRAM memory devices.

There are two factors which limit pad interface performance:

•signal delay to and from the SDRAM memory devices

•skew between the signals.

Note

Process shrinks do not generally improve the performance of the pads. Therefore a memory controller whose performance is limited by the pad interface does not generally run any faster when a smaller process geometry is used.

Pad Interface Timing

A.2 Signal delay

The pads add a large delay and skew to the signals going both off and on chip. This delay is, in part, dependent on the load of the PCB interconnect and the devices to be driven.

The PCB interconnect also add a delay and skew on the signals. Figure A-1 shows an on-chip to off-chip delay for a single signal.

On-chip

MPMCCLK

MPMCDATAOUT[0]

delay

Off-chip

MPMCCLK

MPMCDATAOUT[0]

Figure A-1 On-chip to off-chip delay for a single signal

Pad Interface Timing

A.3 Method to reduce delay

You can reduce signal delay by using appropriately sized pads, and minimizing the load on the pads, for example by reducing the number of memory devices in the system.

If you use more than one output clock, MPMCCLKOUT, it enables the load on the clock to be spread.

A.3.1 Signal skew

Signal skew can be split into static, dynamic and environmental effects.

A.3.2 Static effects

The types of static effects are:

•Routing mismatch. The paths of the different signals might be different.

•Different loading. The signals might be loaded differently.

•Source timing different. The signals might be generated at different times.

A.3.3 Dynamic effects

The types of dynamic effects are:

•Data pattern. The data pattern might affect the time when the signal becomes valid. For example a signal changing from 0 to 1 might take a different time from a signal changing from 1 to 0.

•Simultaneously Switching Outputs (SSO). If a large number of outputs change at the same time it might take more time to reach the valid value than when a small number of signals change.

Figure A-2 on page A-5 shows on-chip to off-chip delay with skew for a single bit of the databus MPMCDATAOUT[0]. Registering this signal on the rising edge of the clock, in this case, captures the data correctly.

On-chip

MPMCCLK

MPMCDATAOUT[0]

delay

Off-chip

MPMCCLK

MPMCDATAOUT[0]

Figure A-2 On-chip to off-chip delay with skew for a single signal

Pad Interface Timing

Figure A-3 shows on-chip to off-chip delay with skew for multiple signals, MPMCDATAOUT[31:0]. You can see that the time when all the signals on the databus are valid at the same time is smaller. In this case registering the group of signals on the rising edge of the clock does not capture the data correctly.

On-chip

MPMCCLK

MPMCDATAOUT[31:0]

delay

Off-chip

MPMCCLK

MPMCDATAOUT[31:0]

Figure A-3 On-chip to off-chip delay with skew for multiple signals

A.3.4 Environmental effects

The above sources of skew are affected by both temperature and voltage. This adds additional skew, as ideally the design works at a high voltage and low temperature, and low voltage and high temperature.