Chapter 5

Static Memory Controller

This chapter describes the Static Memory Controller (SMC). It contains the following sections:

•Static memory device selection on page 5-2

•Write-protection on page 5-3

•Extended wait transfers on page 5-4

•Memory mapped peripherals on page 5-5

•Static memory initialization on page 5-6

•Byte lane control and databus steering for little and big-endian configurations on page 5-28.

Static Memory Controller

5.1Static memory device selection

Table 5-1 shows suggested configurations for the static memory controller with different types of memory devices. These fields are found in the MPMCStaticConfig[n] register, for more information see Chapter 3 Programmer’s Model.

Table 5-1 Static memory controller configurations

a.Enabling the buffers means that any access causes the buffer to be used. Depending on the application, this can provide performance improvements. Generally, devices without async-page-mode support work better with the buffer disabled. Devices with async page-mode support are more efficient with the buffer enabled.

b.SRAM and FLASH memory devices can be write protected if required.

c.Buffering must be disabled when polling the FLASH memories status registers and during writes.

Note

Write buffering can only be enabled if the ordering of transfers is unimportant. This is the case for SRAM. Extended wait and Page mode cannot be enabled simultaneously.

Static Memory Controller

5.2Write-protection

Each memory bank can be configured for write-protection. Usually SRAM is unprotected and ROM devices must be write-protected (to avoid potential bus conflict when performing a write access to ROM), but the P field in the MPMCStaticConfig register can be set to write-protect SRAM as well as ROM devices. If a write access is made to a write-protected memory bank, an error is indicated by the HRESP[1:0] signal. If a write access is made to a memory bank containing ROM devices and the bank is not write-protected, an error indication is not returned, and a write access proceeds as normal. In this case output enable is not brought LOW (active). Depending on the ROM device, this might lead to bus conflict.

Static Memory Controller

5.3Extended wait transfers

The static memory controller supports extremely long transfer times. In normal use the memory transfers are timed using the MPMCStaticWaitRd and MPMCStaticWaitWr registers. These registers enable transfers with up to 32 wait states. However, if an extremely slow static memory device has to be accessed you can enable the MPMCStaticConfig Extended Wait (EW) bit. When this bit is enabled the MPMCStaticExtendedWait register is used to time both the read and write transfers. This register enables transfers to have up to 16368 wait states.

Note

Using extremely long transfer times might mean that SDRAM devices are not refreshed correctly.

Very slow transfers can severely degrade system performance as the external memory interface is tied up for long periods of time. This has detrimental efforts on time critical services, such as interrupt latency and low latency devices, for example video controllers.