Dynamic Memory Controller

6.8Micron MT28F4M16S2 SyncFlash initialization example

You can use the following procedure to initialize Micron MT28S4M16LC SyncFlash (64MB, 4M x16) devices configured to provide a 16-bit bus. HCLK and MPMCLK are 100MHz:

1.Wait for the power to be applied and the clocks have stabilized.

2.Set the RP value in the MPMCDynamicControl register HIGH.

3.Wait 100µs.

4.Program the operational value into the latency register, MPMCDynamicRasCas. The -10 speed grade devices support CAS latency 3 at 100MHz operation. Therefore, 0x0303 must be programmed into the register.

5.Program the operational values into the configuration register, MPMCDynamicConfig. The buffers must be disabled during initialization. For this memory device the fields must be set as shown in Table 6-55.

Table 6-55 Field settings for Micron MT28S4M16LC SyncFlash

The value is 0x14801290.

6.Set the SDRAM Initialization (I) value to MODE in the MPMCDynamicControl register.

7.Program the SyncFlash memories mode register. The mode register enables the following parameters (shown in Table 6-49 on page 6-57) to be programmed:

•burst length

•burst type

•CAS latency

•operating mode

•write burst mode.

Dynamic Memory Controller

A read transaction from the SDRAM memory programs the mode register. The address of the transfer contains the value to be programmed. The mapping from AHB address bus, HADDR, to the SDRAM memories address lines depends on the address mapping value selected in the MPMCDynamicConfig register, in this case 16-bit, 64Mb, 4Mx16, BRC. The row address bits contain the value to be programmed. The bank select signals BA0 and BA1 must both be 0 to program the mode register

Table 6-56 SDRAM mode register settings for Micron SyncFlash SDRAM

8.The value required to program the SyncFlash memories mode register is 0x033. The HADDR to SDRAM memory address mapping is 16-bit 64Mb SDRAM (4Mx16, BRC). The address mapping tables are shown in Address mapping on page 6-4. You can see the SDRAM memory row address bits are mapped to HADDR [20:9]. The SDRAM memory bank address bits are mapped to HADDR [22:21]. Therefore, the address used must be 0x06600.

9.Set the SDRAM Initialization (I) value to NORMAL in the MPMCDynamicControl register.

10.Enable the buffers in MPMCDynamicConfig configuration register. The SDRAM is now ready for normal operation.

Dynamic Memory Controller

6.9Micron SyncFlash commands

Table 6-57 shows the Micron SyncFlash commands supported by the PL172.

Table 6-57 SyncFlash commands

To execute the SyncFlash command set, read or write transfers must be performed while the address is set appropriately. The commands can be found in Table 6-57. CMD1 in the table indicates, HADDR, address bit 27, CMD0 indicates address bit 26.For example to perform a SyncFlash Protect block/confirm command, a write transfer to the memory must be performed to an address where HADDR bit 27 is HIGH, and the rest of the address indicates the bank and row address. The value 0x6001 must be written to the memory.

Note

The buffers must be disabled while executing SyncFlash commands, and enabled for normal operation.

Dynamic Memory Controller