C.4 Pad interface and control signals

Value on

Value

Source/

during

Name

Type

reset

Description

destination

self-

(nPOR)

refresh

MPMCADDROUT[27:0]

Output

Pad

0x0000000

Depends on

Address output. Used for

static

both static and SDRAM

memory

devices.SDRAM memories

accesses

use bits [14:0]. Static

memories use bits [25:0].

MPMCCKEOUT[3:0]

Output

Pad

0xF

0x0

SDRAM clock enables.

Used for SDRAM devices.

MPMCCLKOUT[3:0]

Output

Pad

Follows

Follows

SDRAM clocks. Used for

SDRAM clock out

MPMCCLK

MPMCCLK

SDRAM devices.

MPMCDATAIN[31:0]

Input

Pad

Read data from memory.

Used for the static memory

controller, the dynamic

memory controller and the

TIC.

MPMCDATAOUT[31:0]

Output

Pad

0x00000000

Depends on

Data output to memory.

static

Used for the static memory

memory

controller, the dynamic

accesses

memory controller and the

TIC.

MPMCDQMOUT[3:0]

Output

Pad

0xF

0xF

Data mask output to

SDRAM data mask

SDRAMs. Used for

SDRAM devices and static

memories.

MPMCFBCLKIN[3:0]

Input

Pad

-

-

Fed-back clocks. Used for

SDRAM fed-back clock in

SDRAM devices.

MPMCRPVHHOUT

Output

Pad

0

-

Voltage control for RP

output signal.

MPMCTESTIN

Input

Pad

-

-

This is pin is used to place

Test Mode

the MPMC into TIC test

mode. Used for TIC test.

C-8

Copyright © 2002 ARM Limited. All rights reserved.

ARM DDI 0215A

MultiPort Memory Controller Signal Descriptions

Table C-4 Pad interface and control signal descriptions (continued)

Value on

Value

Source/

during

Name

Type

reset

Description

destination

self-

(nPOR)

refresh

nMPMCBLSOUT[3:0]

Output

Pad

0xF

Depends on

Byte lane select, active

static

LOW, for static memories.

memory

Used for static memory

accesses

devices.

nMPMCCASOUT

Output

Pad

1

1

Column address strobe.

Used for SDRAM devices.

nMPMCDATAOUTEN[3:0]

Output

Pad control

0xF

0xF

Tristate I/O pad output

enable for the byte lanes of

the external memory

databus

MPMCDATA[31:0], active

LOW. Enables the byte

lanes [31:24], [23:16],

[15:8], and [7:0] of the

databus independently.

Used for the static and

dynamic memory

controllers, and the TIC.

nMPMCDYCSOUT[3:0]

Output

Pad

0xF

0xF

SDRAM chip selects. Used

for SDRAM devices.

nMPMCOEOUT

Output

Pad

1

Depends on

Output enable for static

static

memories. Used for static

memory

memory devices.

accesses

nMPMCRASOUT

Output

Pad

1

1

Row address strobe. Used

for SDRAM devices.

nMPMCRPOUT

Output

Pad

0

-

Reset power down to

SyncFlash memory. Used

for the dynamic memory

controller.

nMPMCSTCSOUT[3:0]

Output

Pad

0xF

Depends on

Static memory chip selects.

static

Default active LOW. Used

memory

for static memory devices.

accesses

ARM DDI 0215A

Copyright © 2002 ARM Limited. All rights reserved.

C-9

Value on

Value

Source/

during

Name

Type

reset

Description

destination

self-

(nPOR)

refresh

nMPMCWEOUT

Output

Pad

1

Depends on

Write enable. Used for

Write enable. During test

static

SDRAM and static

mode acts as test acknowledge

memory

memories.

signal

accesses

This signal is used as test

acknowledge

(MPMCTESTACK),

during TIC test mode.The

test bus acknowledge signal

gives external indication

that the test bus has been

granted and also indicates

when a test access has

completed. When

MPMCTESTACK is LOW

the current test vector must

be extended until

MPMCTESTACK

becomes HIGH.

MPMCTESTREQB

Input

Pad

-

-

This pin is used in TIC test

Test bus request B

mode. During test this

signal is used, in

combination with

MPMCTESTREQA, to

indicate the type of test

vector that is applied in the

following cycle. The test

bus acknowledge signal

gives external indication

that the test bus has been

granted and also indicates

when a test access has

completed. When

MPMCTESTACK is

LOW, the current test vector

must be extended until

MPMCTESTACK

becomes HIGH.

C-10

Copyright © 2002 ARM Limited. All rights reserved.

ARM DDI 0215A

MultiPort Memory Controller Signal Descriptions

Table C-4 Pad interface and control signal descriptions (continued)

Value on

Value

Source/

during

Name

Type

reset

Description

destination

self-

(nPOR)

refresh

MPMCTESTREQA Test bus

Input

Pad

-

-

This pin is used in TIC test

request A

mode. In test mode, this pin

is the test bus request A

input signal and is required

as a dedicated device pin.

ARM DDI 0215A

Copyright © 2002 ARM Limited. All rights reserved.

C-11