C.5 Test Interface Controller (TIC) signals

Name

Type

Source/

Description

destination

HADDRTIC[31:0]

Output

AHB slave

The 32-bit AHB address bus.

Address bus

layer

HBUSREQTIC

Output

AHB arbiter

A signal from the TIC to the bus arbiter which indicates that it

Bus request

requires the bus.

HBURSTTIC[2:0]

Output

AHB slave

Indicates if the transfer forms part of a burst. The TIC always

Burst type

layer

performs incrementing bursts of unspecified length.

HGRANTTIC

Input

AHB arbiter

This signal indicates that the TIC is currently the highest priority

Bus Grant

master. Ownership of the address and control signals changes at the

end of a transfer when HREADY is HIGH, so the TIC controller

gains access to the bus when both HREADY and HGRANTTIC are

HIGH.

HLOCKTIC

Output

AHB arbiter

When HIGH, this signal indicates that the TIC requires locked access

Locked transfers

to the bus. No other master must be granted the bus until this signal is

LOW.

HPROT[3:0]

Output

AHB slave

The protection control signals indicate if the transfer is an opcode

Protection Control

layer

fetch or data access, as well as if the transfer is a supervisor mode

access or a User mode access. These signals also indicate if the

current access is cachable or bufferable.

HRDATATIC[31:0]

Input

AHB master

The read databus is used to transfer data from the AHB slave to the

Read databus

layer

TIC controller during read operations.

HREADYINTIC

Input

AHB slave

When HIGH, the HREADYIN signal indicates that a transfer has

Transfer done

layer

finished on the bus. This signal can be driven LOW to extend a

transfer.

HRESPTIC[1:0]

Input

AHB slave

The transfer response provides additional information on the status of

Transfer response

layer

a transfer. Four different responses are provided, OKAY, ERROR,

RETRY, and SPLIT.

HSIZETIC[2:0]

Output

AHB slave

Indicates the size of the transfer, which is typically byte (8-bit),

Transfer size

layer

halfword (16-bit), or word (32-bit). The TIC does not support larger

transfer sizes.

C-12

Copyright © 2002 ARM Limited. All rights reserved.

ARM DDI 0215A

MultiPort Memory Controller Signal Descriptions

Table C-5 TIC signal descriptions (continued)

Name

Type

Source/

Description

destination

HTRANSTIC[1:0]

Output

AHB slave

Indicates the type of the current transfer, which can be

Transfer type

layer

NONSEQUENTIAL, SEQUENTIAL, IDLE, or BUSY. The TIC does

not use the BUSY transfer type.

HWDATATIC[31:0]

Output

AHB slave

The write databus is used to transfer data from the master to the bus

Write databus

layer

slaves during write operations.

HWRITETIC

Output

AHB slave

When HIGH, this signal indicates a write transfer and when LOW a

Transfer direction

layer

read transfer.

ARM DDI 0215A

Copyright © 2002 ARM Limited. All rights reserved.

C-13

Table C-6 Scan test signal descriptions

Name

Type

Source/

Description

destination

SCANENABLE

Input

Test controller

Scan enable

SCANINHCLK

Input

Test controller

Scan data input for HCLK scan chain

SCANINMPMCFBCLKIN0

Input

Test controller

Scan in for MPMCFBCLKIN0 scan chain

SCANINMPMCFBCLKIN1

Input

Test controller

Scan in for MPMCFBCLKIN1 scan chain

SCANINMPMCFBCLKIN2

Input

Test controller

Scan in for MPMCFBCLKIN2 scan chain

SCANINMPMCFBCLKIN3

Input

Test controller

Scan in for MPMCFBCLKIN3 scan chain

SCANINMPMCCLK

Input

Test controller

Scan in for MPMCCLK scan chain

SCANOUTHCLK

Output

Test controller

Scan data output for HCLK scan chain

SCANOUTMPMCFBCLKIN0

Output

Test controller

Scan out for MPMCFBCLKIN0 scan chain

SCANOUTMPMCFBCLKIN1

Output

Test controller

Scan out for MPMCFBCLKIN1 scan chain

SCANOUTMPMCFBCLKIN2

Output

Test controller

Scan out for MPMCFBCLKIN2 scan chain

SCANOUTMPMCFBCLKIN3

Output

Test controller

Scan out for MPMCFBCLKIN3 scan chain

SCANOUTMPMCCLK

Output

Test controller

Scan out for MPMCCLK scan chain

C-14

Copyright © 2002 ARM Limited. All rights reserved.

ARM DDI 0215A

A

C

Dynamic memory controller register

banks 2-3, 2-4

Access sequencing and memory width

Clock feedback

10-19

Dynamic memory devices supported

5-6, 6-3

Clock strategy

10-17

1-4

Access to memory banks, 16 or 32-bit

Command sequencer 2-3, 2-4

devices 5-24

Connecting

Access to memory banks, 8-bit devices

mixed width memory devices 10-25

E

5-23

SDRAM and SRAM memory

Address mapping 6-4

devices 10-26

Elimination of floating bytes

5-27

AHB memory interface

9-4

x16 SDRAM devices

10-23

Entry into TIC test mode

8-3

AHB register interface

9-2

x32 SDRAM devices

10-24

Example system 2-10

AHB slave memory interface

2-5, 2-6

x8 SDRAM devices 10-21

Extended wait transfers

5-4

AHB slave register interface

2-4

External bus

2-10

Asynchronous page mode read ROM

D

5-13

F

Data buffers 2-6

B

Data bus steering

5-28

Features, PrimeCell MPMC

1-2

Deep sleep mode

2-12

Flash devices

1-6

Block diagram

2-2

Dynamic Memory Controller 6-1

Flash memory

5-19

Bus turnaround

5-19

Dynamic memory controller

Four fed-back clocks 10-19

Byte lane control 5-23, 5-28

command descriptions

6-53

Functional blocks 2-1

ARM DDI 0215A

Copyright © 2002 ARM Limited. All rights reserved.

Index-1

G

MPMC test harness

4-2

MPMCStatus register

3-10

MPMC test strategy

4-2

Generic SDRAM

MPMC timing 10-14

O

initialization example 6-54

6-54

MPMCConfig register

3-11

Generic SDRAM initialization

MPMCControl register

3-7

MPMCDynamicConfig[0,1,2,3]

Off-chip signals

10-2

H

register 3-22

Off-chip timing

10-16

MPMCDynamicControl register

3-12

On-chip signals

9-2

MPMCDynamicRefresh register

3-15

On-chip timing

10-15

High performance systems 10-20

MPMCDynamictAPR register

3-17

Output clocks 10-19

MPMCDynamictDAL register

3-18

Output enable programmable delay 5-7

I

MPMCDynamictMRD register

3-21

MPMCDynamictRAS register

3-16

P

Initialization

MPMCDynamictRC register

3-19

MPMCDynamictRFC register

3-19

generic SDRAM 6-54

MPMCDynamictRP register

3-16

Pad interface 2-7

Low-Power SDRAM

6-59

MPMCDynamictRRD register

3-20

Pad interface block diagram

2-8

SDRAM

6-56

MPMCDynamictSREX register

3-17

Pad interface signals C-8

static memory 5-6

MPMCDynamictWR register

3-18

Page mode Flash devices

1-6

SyncFlash

6-62

MPMCDynamictXSR register

3-20

Page mode ROM devices

1-6

Internal bus

2-11

MPMCITCR register

4-4

Pin count reduction 10-4, 10-5

MPMCITIP register

4-4

Power management connectivity 9-5

L

MPMCITOP register

4-6

Power-on reset memory map

2-16

MPMCPCellID0-3 register

3-38

PrimeCell MPMC

MPMCPeriphID0 register

3-36

functional blocks 2-1

Locks and semaphores

2-13

MPMCPeriphID0-3 register

3-35

register descriptions

3-7

Low-power SDRAM

MPMCPeriphID1 register

3-37

signal descriptions

A-1, B-1, C-1

initialization example 6-59

MPMCPeriphID2 register

3-37

Priority 2-6

Low-Power SDRAM devices

1-5

MPMCPeriphID3 register

3-38

Protected memory areas

2-5

Low-Power SDRAM initialization

MPMCPeriphID4 register

3-34

6-59

MPMCPeriphID4-7 register

3-33

R

Low-power sleep modes

2-12

MPMCPeriphID5-7 register

3-34

MPMCRasCas[0,1,2,3] register

3-26

M

MPMCStaticConfig[0,1,2,3] register

Reducing data bus width

10-4

3-27

Register descriptions 3-7

MPMCStaticExtendedWait register

Registers

Memory bank select 2-15

3-21

MPMCConfig

3-11

Memory connection diagram

5-24

MPMCStaticWaitOen[0,1,2,3] register

MPMCControl

3-7

Memory mapped peripherals

5-5

3-30

MPMCDynamicConfig[0,1,2,3]

Memory transaction endianness

2-5

MPMCStaticWaitPage[0,1,2,3]register

3-22

Memory transaction size 2-5

3-32

MPMCDynamicControl

3-12

Memory transfer state machine

2-3,

MPMCStaticWaitRd[0,1,2,3] register

MPMCDynamicRefresh

3-15

2-4

3-31

MPMCDynamictAPR

3-17

Micron MT28F4M16S2 SyncFlash

MPMCStaticWaitTurn[0,1,2,3]register

MPMCDynamictDAL

3-18

initialization example 6-62

3-33

MPMCDynamictMRD 3-21

Micron MT48LC4M16A2 SDRAM

MPMCStaticWaitWen[0,1,2,3]register

MPMCDynamictRAS

3-16

initialization example 6-56

3-30

MPMCDynamictRC

3-19

Micron SyncFlash commands

6-64

MPMCStaticWaitWr[0,1,2,3] register

MPMCDynamictRFC

3-19

Miscellaneous and clock signals

C-6

3-32

MPMCDynamictRP

3-16

Index-2

Copyright © 2002 ARM Limited. All rights reserved.

ARM DDI 0215A

MPMCDynamictRRD

3-20

scan test control C-14

MPMCStaticWaitOen

3-30

MPMCDynamictSREX 3-17

TIC C-12

MPMCStaticWaitPage

3-32

MPMCDynamictWR

3-18

SRAM devices 1-6

MPMCStaticWaitRd 3-31

MPMCDynamictXSR

3-20

Static memory controller register banks

MPMCStaticWaitTurn

3-33

MPMCITCR

4-4

2-3, 2-4

MPMCStaticWaitWen

3-30

MPMCITIP

4-4

Static memory device selection 5-2

MPMCStaticWaitWr

3-32

MPMCITOP

4-6

Static memory devices supported

1-6

MPMCPCellID0-3 3-38

Static memory initialization

5-6

MPMCPeriphID0

3-36

Static memory read control

5-7

MPMCPeriphID0-3 3-35

Static memory write control

5-15

MPMCPeriphID1

3-37

Supported dynamic memory devices

MPMCPeriphID2

3-37

1-4

MPMCPeriphID3

3-38

Supported static memory devices

1-6

MPMCPeriphID4

3-34

SyncFlash commands 6-64

MPMCPeriphID4-7 3-33

SyncFlash initialization

6-62

MPMCPeriphID5-7 3-34

Synchronous Flash devices 1-5

MPMCRasCas[0,1,2,3] 3-26

System interconnection diagram

9-3

MPMCStaticConfig[0,1,2,3]

3-27

MPMCStaticExtendedWait 3-21

T

MPMCStaticWaitOen[0,1,2,3]

3-30

MPMCStaticWaitPage[0,1,2,3]

Termination of off chip signals

10-20

3-32

Test harness

4-2

MPMCStaticWaitRd[0,1,2,3]

3-31

Test Interface Controller (TIC) 2-9, 8-2

MPMCStaticWaitTurn[0,1,2,3]

Test registers

4-4

3-33

Test strategy

4-2

MPMCStaticWaitWen[0,1,2,3]

TIC block diagram 2-9

3-30

TIC test connectivity 9-4

MPMCStaticWaitWr[0,1,2,3]

3-32

TIC test mode 8-3

MPMCStatus 3-10

Timed out transactions

2-5

test 4-4

Timing

Removing functionality 10-5

MPMC 10-14

Reset controller connectivity 9-4

off-chip 10-16

ROM devices 1-6

on-chip 10-15

Row, bank, column 6-5

ARM DDI 0215A

Copyright © 2002 ARM Limited. All rights reserved.

Index-3

Index-4

Copyright © 2002 ARM Limited. All rights reserved.

ARM DDI 0215A