Static Memory Controller

5.6Byte lane control

The PrimeCell MPMC generates byte lane control signals nMPMCBLSOUT[3:0] according to:

•little or big-endian operation

•AMBA transfer width, indicated by HSIZE[2:0]

•external memory bank databus width, defined within each control register

•the decoded HADDR[1:0] value for write accesses only.

Word transfers are the largest size transfers supported by the MPMC. Any access attempted with a size greater than a word causes an ERROR response to be generated. Each memory chip select can be 8, 16, or 32 bits wide. The type of memory used determines how the nMPMCWEOUT and nMPMCBLSOUT signals are connected to provide byte, halfword and word access. For read accesses, you must control the nMPMCBLSOUT signals by driving them either all HIGH, or all LOW. This is done by programming the Byte Lane State (PB) bit within the MPMCStaticConfig[n] register. Accesses to memory banks constructed from 8-bit or non byte-partitioned memory devices and Accesses to memory banks constructed from 16 or 32-bit memory devices on page 5-24 explain why different connections are required, in respect of nMPMCWEOUT and nMPMCBLSOUT[3:0], for different memory configurations.

5.6.1 Accesses to memory banks constructed from 8-bit or non byte-partitioned memory devices

For memory banks constructed from 8-bit or non byte-partitioned memory devices, it is important that the Byte Lane State (PB) bit is cleared to 0 within the respective memory bank control register. This forces all nMPMCBLSOUT[3:0] lines HIGH during a read access as the byte lane selects are connected to the device write enables.

Figure 5-16 on page 5-24 shows 8-bit memory being used to configure memory banks that are 8, 16, and 32-bits wide. In each of these configurations, the nMPMCBLSOUT[3:0] signals are connected to write enable (nWE) inputs of each 8-bit memory. The nMPMCWEOUT signal from the PrimeCell MPMC is not used. For write transfers, the relevant nMPMCBLSOUT[3:0] byte lane signals are asserted LOW, and steer the data to the addressed bytes. For read transfers, all of the nMPMCBLSOUT[3:0] lines are deasserted HIGH, which enables the external bus to be defined for at least the width of the accessed memory.

Static Memory Controller

Figure 5-16 Memory banks constructed from 8-bit memory

5.6.2Accesses to memory banks constructed from 16 or 32-bit memory devices

For memory banks constructed from 16 or 32-bit memory devices, it is important that the Byte Lane Select (PB) bit is set to 1 within the respective memory bank control register. This asserts all nMPMCBLSOUT[3:0] lines LOW during a read access as during a read all bytes of the devices must be selected to avoid undriven byte lanes on the read data value. In the case of 16 and 32-bit wide memory devices, byte select signals exist and these must be appropriately controlled, as shown in Figure 5-17 and Figure 5-18 on page 5-25.

Figure 5-17 Memory banks constructed from 16-bit memory

Static Memory Controller

nMPMCSTCSOUT nCE

nMPMCOEOUT nOE

nMPMCWEOUT nWE

nMPMCBLSOUT[3] nB3

nMPMCBLSOUT[2] nB2

nMPMCBLSOUT[1] nB1

nMPMCBLSOUT[0] nB0

MPMCDATA[31:0] IO[31:0]

32-bit bank consisting of one 32-bit device

Figure 5-18 Memory bank constructed from 32-bit memory

Figure 5-19 on page 5-26 shows connections for a typical memory system with different data width memory devices.

Static Memory Controller

Figure 5-19 Typical memory connection diagram

Static Memory Controller

5.6.3Elimination of floating bytes on the external interface

The PrimeCell MPMC uses the programmed external memory width of each bank and the endianness to determine which remaining bytes it requires to drive to ensure that the external bus is never floating. The input/output pads for the external write databus lines are controlled by nMPMCDATAOUTEN[3:0] as shown in Table 5-2. Data is driven out on MPMCDATAOUT[31:0] when nMPMCDATAOUTEN is asserted LOW.

Table 5-2 MPMCDATAOUT[31:0] controlled by nMPMCDATAOUTEN[3:0]