System Connectivity

9.3Example system

This section shows an example system. The system illustrates the memory controller integration issues. See Figure 9-5 for a block diagram of the example system.

Figure 9-5 Example system

System Connectivity

9.3.1AHB bus 0

The highest priority MPMC AHB memory port, port 0, is connected to high priority, low latency peripheral, in this case a LCD controller.

9.3.2AHB bus 1

The next highest priority MPMC AHB memory port, port 1, is connected to the next highest priority peripheral, in this case a DMA controller.

9.3.3AHB bus 2

MPMC AHB memory port 2, is connected to a DMA controller.

9.3.4AHB bus 3

The AHB memory port (lowest priority), the AHB register port, and the AHB Tic port of the MPMC are all connected to AHB bus 3. The ARM processor is also connected to this bus. The ARM processor is therefore able to program the MPMC and to access external memory. The ARM processor can also be production tested using TIC test patterns.

Note

Some ARM processors use the TIC interface for production test.

9.3.5Power Management Unit

The major components of the Power Management Unit (PMU) are:

•Reset controller

•Refresh controller on page 9-12

•Clock select on page 9-12.

Reset controller

The reset controller generates the power-on-reset, nPOR, and AMBA reset signal,

HRESETn.

The MPMCBIGENDIAN, MPMCSTCS1MW[1:0], and MPMCSTCS[3:0]POL signals are generated by registering the value of a number of inputs to the chip when the power-on reset goes inactive. These input signals are reused during normal operation.

System Connectivity

Refresh controller

The refresh controller can place the SDRAM memory devices into self-refresh mode by using the MPMCSREFREQ and MPMCSREFACK signals.

Clock select

The clock select logic is used to select the various clocks. In TIC test mode, when MPMCTESTIN is HIGH, HCLK and MPMCCLK must operate at no more than 10MHz.

9.3.6MPMC off-chip signals

The MPMC off-chip signals are:

•Functional mode signals

•Test mode signals.

Functional mode signals

The system has a 16-bit external databus MPMCDATA[15:0].

MPMCDATAOUT[15:0] and MPMCDATAIN[15:0] are connected to bidirectional tristate pads. The direction of these pads is controlled by MPMCDATAEN[1:0].

It is recommended that you use clock pads, if available, for the clock signals

MPMCCLKOUT[3:0] and MPMCFBCLKIN[3:0].

The output signals, for example MPMCADDROUT[27:0], must be skew balanced with the databus. This can be performed by selecting appropriate pad cells. One possible way is to use the same bidirectional pads for the output signals as used for the data signals.

The input signals need not be skew balanced and so an appropriate input pad must be chosen.

Test mode signals

This example system requires the use of the TIC controller for ARM production test. The TIC controller requires a 32-bit databus, MPMCDATA[31:0], and three control signals, MPMCTESTREQA, MPMCTESTREQB and MPMCTESTACK.

MPMCTESTACK is multiplexed with the nMPMCWEOUT signal. The MPMCTESTREQA, MPMCTESTREQB and upper 16-bits of the databus, MPMCDATA[31:16], signals are required in test mode. To minimize the number of pads used these signals can be multiplexed with other signals.