Chapter 10

Off-chip Connectivity

This chapter provides examples of how external memory can be connected to the MPMC. It contains the following sections:

•Off-chip signals on page 10-2

•Pin count reduction by reducing databus width on page 10-4

•Pin count reduction by removing functionality on page 10-5

•Address pin reduction on page 10-9

•Chip select pin reduction on page 10-10

•Device support on page 10-11

•Multiplexing static and dynamic memory pins on page 10-12

•Reducing pin count by multiplexing MPMC pins on page 10-13

•About MPMC timing on page 10-14

•On-chip timing path on page 10-15

•Off-chip timing path on page 10-16

•Clock strategy on page 10-17

•Clock ratios on page 10-18

•Memory clock and fed-back clock strategy on page 10-19.

Off-chip Connectivity

10.1Off-chip signals

Table 10-1 shows the pins that are required to be bonded out. For a 32-bit wide external databus 86 pins are required, for a 16-bit external databus 70 pins are required.

Table 10-1 External pins

The signals in Table 10-2 on page 10-3 might also have to be bonded out. Some of the signals can be multiplexed.

Off-chip Connectivity

The MPMCTESTREQA and MPMCTESTREQB signals are only required in TIC test mode and can therefore be multiplexed with other signals.

The MPMCRPVHHOUT signal is only required to be bonded out if:

•Micron SyncFlash support is required,

•high voltage VHH nRP support is required and,

•the high voltage generator is not on the chip.

.

Table 10-2 Multiplexed pins

Off-chip Connectivity

10.2Pin count reduction by reducing databus width

The databus width can be reduced from 32 bits to 16 bits. Using a HCLK to MPMCCLK ratio of 1:1, with a 16-bit bus impacts performance. Using a MPMCCLK that is twice the frequency of HCLK, with a 16-bit bus, provides similar performance to a design with a 32-bit databus.