Appendix B
Troubleshooting
This appendix describes how to troubleshoot the ARM PrimeCell MPMC block. It contains the following section:
•Troubleshooting on page B-2.
ARM DDI 0215A |
Copyright © 2002 ARM Limited. All rights reserved. |
B-1 |
Troubleshooting
B.1 Troubleshooting
Table B-1 lists typical problems and the suggested remedy.
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Table B-1 Troubleshooting |
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Problem |
Suggested remedy |
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Static memory operates correctly, but |
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Ensure that the SDRAM memory is |
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accessing dynamic memory does not |
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initialized correctly. The appropriate address |
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work. |
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mapping, burst size, and CAS latency must |
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be programmed. |
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Note |
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During initialization the buffers |
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(MPMCDynamicConfig, B = 0) must be |
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disabled, and CKE |
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(MPMCDynamicControl, CD = 1) must be |
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HIGH. |
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• |
Ensure that the buffers are enabled during |
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normal operation (MPMCDynamicConfig, |
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B = 1). |
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If the memory is being clocked at twice the |
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frequency of HCLK. Ensure that HCLK |
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and MPMCCLK are synchronous, and that |
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their positive clock edges are aligned. |
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How must HSELMPMCxG and |
HSELMPMCxG must go active whenever there is |
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HSELMPMCxS[7:0] function? |
an access to the PrimeCell MPMC. Together with |
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HSELMPMCxG going active, the relevant bit of |
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HSELMPMCxS[7:0] must go active.
HSELMPMCxS[7:0] indicates which memory chip select the transfer is for.
B-2 |
Copyright © 2002 ARM Limited. All rights reserved. |
ARM DDI 0215A |
Appendix C
MultiPort Memory Controller Signal
Descriptions
This appendix describes the signals that interface with the ARM PrimeCell MPMC block. It contains the following sections:
•AHB register signals on page C-2
•AHB memory signals on page C-4
•Miscellaneous and clock signals on page C-6
•Pad interface and control signals on page C-8
•Test Interface Controller (TIC) signals on page C-12
•Scan test signals on page C-14.
ARM DDI 0215A |
Copyright © 2002 ARM Limited. All rights reserved. |
C-1 |
MultiPort Memory Controller Signal Descriptions
C.1 AHB register signals
Table C-1 describes the AHB register signals.
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Table C-1 AHB register signal descriptions |
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Name |
Type |
Source/ |
Description |
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destination |
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HADDRREG[11:2] |
Input |
AHB master |
The AHB address bus. |
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Address bus |
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layer |
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HCLK |
Input |
Clock source |
This clock times all bus transfers. All signal timings are |
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Bus clock |
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related to the rising edge of HCLK. |
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HRDATAREG[29:0] |
Output |
AHB master |
The read databus is used to transfer data from the |
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Read databus |
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layer |
MPMC to the bus master during read operations. |
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HREADYINREG |
Input |
AHB slave |
When HIGH, the HREADYIN signal indicates that a |
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Transfer done |
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layer |
transfer has finished on the bus. This signal can be |
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driven LOW to extend a transfer. An alternate slave |
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generates this signal. |
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HREADYOUTREG |
Output |
AHB master |
When HIGH, the HREADYOUT signal indicates that |
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Transfer done |
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layer and AHB |
a transfer has finished on the bus. This signal can be |
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slave layer |
driven LOW to extend a transfer. |
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HRESETn |
Input |
Reset controller |
The bus reset signal is active LOW and is used to reset |
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Reset |
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the system and the bus. |
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HRESPREG[1:0] |
Output |
AHB master |
The transfer response provides additional information |
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Transfer response |
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on the status of a transfer. Four different responses are |
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provided, OKAY, ERROR, RETRY, and SPLIT. The |
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SDRAM Controller can respond with either the OKAY |
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or ERROR responses. The ERROR response is |
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generated when the transfer size is not 32-bits wide. |
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HSELMPMCREG |
Input |
AHB decoder |
MPMC controller register select signal. This signal |
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Slave select |
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indicates an access to the memory controllers control |
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registers. |
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HSIZEREG[2:0] |
Input |
AHB master |
Indicates the size of the transfer, which is typically byte |
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Transfer size |
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layer |
(8-bit), halfword (16-bit), or word (32-bit). Only word |
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(32-bit) transfers are allowed, (HSIZE[2:0] = 0b010) to |
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access the MPMC registers. Transfer sizes other than |
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32-bits generate an ERROR response. |
C-2 |
Copyright © 2002 ARM Limited. All rights reserved. |
ARM DDI 0215A |
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MultiPort Memory Controller Signal Descriptions |
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Table C-1 AHB register signal descriptions (continued) |
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Name |
Type |
Source/ |
Description |
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destination |
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HTRANSREG |
Input |
AHB master |
Indicates the type of the current transfer, which can be |
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Transfer type |
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layer |
NONSEQUENTIAL, SEQUENTIAL, IDLE, or BUSY. |
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Only HTRANS[1] is used. Indicating if a transfer is |
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required or not. |
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HWDATAREG29TO28[29:28] |
Input |
AHB master |
The write databus is used to transfer data from the |
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Write databus |
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layer |
master to the bus slaves during write operations. |
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HWDATAREG26 |
Input |
AHB master |
The write databus is used to transfer data from the |
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Write databus |
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master to the bus slaves during write operations. |
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HWDATAREG24TO22[24:22] |
Input |
AHB master |
The write databus is used to transfer data from the |
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Write databus |
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layer |
master to the bus slaves during write operations. |
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HWDATAREG20TO0[20:0] |
Input |
AHB master |
The write databus is used to transfer data from the |
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Write databus |
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layer |
master to the bus slaves during write operations. |
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HWRITEREG |
Input |
AHB master |
When HIGH this signal indicates a write transfer and |
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Transfer direction |
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layer |
when LOW a read transfer. |
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ARM DDI 0215A |
Copyright © 2002 ARM Limited. All rights reserved. |
C-3 |