Chapter 7

Common Memory Transactions

This chapter describes transactions for both dynamic and static memory accesses. It contains the following section:

•Static and dynamic memory transaction latency on page 7-2.

Common Memory Transactions

7.1Static and dynamic memory transaction latency

This section describes common transactions for static and dynamic memory accesses in the following subsections:

•Summary

•Miscellaneous transactions

•Buffer hit transactions on page 7-4.

7.1.1Summary

The following values assume CAS latency 2 SDRAM, where CAS, RAS and Precharge (tRP) are 2 clock cycles.

The latency heading shows the latency seen by the AHB interface, where the request is dealt with immediately.

7.1.2Miscellaneous transactions

Miscellaneous transactions are described in:

•Write transfer to write protected chip select

•Auto refresh cycle on page 7-3.

Write transfer to write protected chip select

Figure 7-1 on page 7-3 shows a write transaction to a write protected bank. The MPMC responds by placing an ERROR response on HRESP[1:0].

Common Memory Transactions

Figure 7-1 A write transfer to a write protected chip select

Auto refresh cycle

Figure 7-2 shows an auto-refresh cycle.

Figure 7-2 An SDRAM auto-refresh cycle

Common Memory Transactions

7.1.3Buffer hit transactions

The following section provides the access times for read and write transfers that hit the buffers.

Both static and dynamic transfers that hit the buffer have the timings provided below.

The latency values provided show the latency seen by the AHB interface, where the request is dealt with immediately. However, for write accesses the data is written to memory later.

Read access timing

Nonsequential transfers (HTRANS=NONSEQ) have a latency of two cycles. Sequential transfers (HTRANS=SEQ), including burst transfers, have a transfer latency of one cycle if they hit a previously accessed buffer. If the buffer was not previously opened the transfer takes two cycles.

Write access timing

Nonsequential transfers (HTRANS=NONSEQ) have a latency of two cycles. Sequential transfers (HTRANS=SEQ) including burst transfers have a transfer latency of one cycle if they hit a previously accessed buffer. If the buffer was not previously opened the transfer takes two cycles.

Table 7-1 shows the buffer access latency.

Table 7-1 Buffer access latency

Common Memory Transactions

Table 7-1 Buffer access latency (continued)

7.1.4Buffer hit transaction waveforms

Figure 7-3 shows a four word INCR burst, or INCR4, or WRAP4 burst read transfers that hit the buffer. The waveform shows the case where all transfers hit the same quad word of data.

HCLK

HWRITE

HREADYOUT

Figure 7-3 An INCR, INCR4, or WRAP4 burst read transfer, buffer hit

Common Memory Transactions

Figure 7-4 shows three sequential reads, of burst type SINGLE from a buffer. The waveform shows the case where all transfers hit the same quad word of data.

HCLK

HWRITE

HREADYOUT

Figure 7-4 Three sequential reads, burst type SINGLE, read transfer, buffer hit

Common Memory Transactions

Figure 7-5 shows three nonsequential reads, of burst type SINGLE from a buffer.

HCLK

HWRITE

HREADYOUT

Figure 7-5 Three nonsequential reads, burst type SINGLE, read transfer, buffer hit

Common Memory Transactions

Figure 7-6 shows an INCR8, or WRAP8 burst read transfers that hit the buffer. The waveform shows the case where transfers start on a quad word boundary.

HCLK

Figure 7-6 An INCR8 or WRAP8 burst read transfer, buffer hit

Common Memory Transactions

Figure 7-7 shows two simultaneous INCR, INCR4, or WRAP4 burst read transfers which hit the buffer. The waveform shows the case where transfers start on a quad word boundary.

Figure 7-7 Two simultaneous INCR, INCR4, or WRAP4 burst read transfer, buffer hit

Common Memory Transactions

Figure 7-8 shows a four word INCR, INCR4, or WRAP4 burst write transfer to a buffer. The waveform shows the case where all transfers hit the same quad word of data. The data is written to memory later.

HCLK

HWRITE

HREADYOUT

Figure 7-8 Four word INCR, INCR4, or WRAP4 burst write

Common Memory Transactions

Figure 7-9 shows three sequential write transfers to a buffer. The waveform shows the case where all transfers hit the same quad word of data. The data is written to memory later.

HCLK

HWRITE

HREADYOUT

Figure 7-9 Three sequential write transfers

Common Memory Transactions

Figure 7-10 shows three nonsequential write transfers to a buffer. The data is written to memory later.

HCLK

HWRITE

HREADYOUT

Figure 7-10 Three nonsequential write transfers

Common Memory Transactions

Figure 7-11 shows an INCR8 or WRAP8 burst write transfer to a buffer. The waveform shows the case where transfers start on a quad word boundary.The data is written to memory later.

HCLK

Figure 7-11 INCR8 or WRAP8 burst write

Common Memory Transactions

Figure 7-12 shows two simultaneous INCR, INCR4, or WRAP4 burst write transfers that hit the buffer. The waveform shows the case where transfers start on a quad word boundary.

Figure 7-12 Two simultaneous INCR, INCR4, or WRAP4 burst write transfer, buffer hit