Off-chip Connectivity

10.8Reducing pin count by multiplexing MPMC pins

Multiplexing MPMC pins has a detrimental effect on pad interface performance. This is because both on and off-chip loading is increased.

Off-chip Connectivity

10.9About MPMC timing

The on-chip path (the path from the MPMC to the pads), and the off-chip path (the path from the chips I/O pins to the memory devices) are critical for high-speed operation.

Off-chip Connectivity

10.10 On-chip timing path

To enable high-speed operation:

•The skew between the MPMC pad interface output signals should be minimized. This is achieved by:

—the MPMC providing four output clocks, MPMCCLKOUT[3:0], to reduce clock signal loading

—the MPMC registering all the output signals before they are sent off chip to minimize skew between the signals

—The system designer situating the MPMC as close to the pads as possible to minimize signal delay and skew

—the system designer not multiplexing the MPMC output signals, because this unnecessarily loads the off-chip signals

—the system designer using the appropriate strength pads for the output signals.

•The skew between the MPMC pad interface input signals should be minimized. This is achieved by:

—the MPMC using a fed-back clock that is ideally fed-back from the memory devices clock pin

—the MPMC providing four fed-back clocks, MPMCFBCLKIN[3:0], to better track the delays of the return data path

—the MPMC registering the input signals, using the MPMCFBCLKIN signals

—the system designer situating the MPMC as close to the pads as possible to minimize signal delay and skew

—the system designer not multiplexing the MPMC input signals, because this unnecessarily loads the signals and can skew the signals

—the system designer using the appropriate strength pads for the input signals.

Off-chip Connectivity

10.11 Off-chip timing path

You must minimize the skew between the various signals during PCB routing.The off-chip path from the ASIC pads to the dynamic memory devices must be as lightly loaded as possible to enable high-speed operation. Therefore, you must minimize the number of memory devices for high-speed operation.

For systems that require a large number of memory devices, additional buffering of the I/O signals might be required. For example, the signals to the static memory devices can be buffered. This adds additional delay when accessing static memories, but enables the dynamic devices to run at a higher speed.