- •Contents
- •List of Tables
- •List of Figures
- •Preface
- •About this document
- •Feedback
- •Introduction
- •1.1 About the ARM PrimeCell MultiPort Memory Controller (PL172)
- •1.2 Supported dynamic memory devices
- •1.3 Supported static memory devices
- •Functional Overview
- •2.1 PrimeCell MPMC functional description
- •2.2 Overview of a PrimeCell MPMC, ASIC, or ASSP system
- •2.3 Low power operation
- •2.4 Lock and semaphores
- •2.5 Arbitration
- •2.6 Memory bank select
- •2.7 Memory map
- •Programmer’s Model
- •3.1 About the programmer’s model
- •3.2 Register descriptions
- •Programmer’s Model for Test
- •4.1 PrimeCell MPMC test harness overview
- •4.2 Scan testing
- •4.3 Test registers
- •Static Memory Controller
- •5.1 Static memory device selection
- •5.2 Write-protection
- •5.3 Extended wait transfers
- •5.4 Memory mapped peripherals
- •5.5 Static memory initialization
- •5.6 Byte lane control
- •5.7 Byte lane control and databus steering for little and big-endian configurations
- •Dynamic Memory Controller
- •6.1 Write-protection
- •6.2 Access sequencing and memory width
- •6.3 Address mapping
- •6.4 Dynamic memory controller command descriptions
- •6.5 Generic SDRAM initialization example
- •6.6 Micron MT48LC4M16A2 SDRAM initialization example
- •6.8 Micron MT28F4M16S2 SyncFlash initialization example
- •6.9 Micron SyncFlash commands
- •Common Memory Transactions
- •7.1 Static and dynamic memory transaction latency
- •Test Interface Controller
- •8.1 About TIC
- •8.2 Sequence of events leading to entry into TIC test mode
- •System Connectivity
- •9.2 Self-refresh entry
- •9.3 Example system
- •Off-chip Connectivity
- •10.2 Pin count reduction by reducing databus width
- •10.3 Pin count reduction by removing functionality
- •10.4 Address pin reduction
- •10.5 Chip select pin reduction
- •10.6 Device support
- •10.7 Multiplexing static and dynamic memory pins
- •10.8 Reducing pin count by multiplexing MPMC pins
- •10.9 About MPMC timing
- •10.10 On-chip timing path
- •10.11 Off-chip timing path
- •10.12 Clock strategy
- •10.13 Clock ratios
- •10.14 Memory clock and fed-back clock strategy
- •Pad Interface Timing
- •A.1 Overview
- •A.2 Signal delay
- •A.3 Method to reduce delay
- •A.4 Methods to reduce skew
- •A.5 Methods to minimize the effects of delay and skew
- •A.6 Example SDRAM memory timing diagram
- •A.7 SDRAM memory timing paths
- •Troubleshooting
- •B.1 Troubleshooting
- •C.1 AHB register signals
- •C.2 AHB memory signals
- •C.3 Miscellaneous and clock signals
- •C.4 Pad interface and control signals
- •C.5 Test Interface Controller (TIC) signals
- •C.6 Scan test signals
Off-chip Connectivity
10.3Pin count reduction by removing functionality
You can reduce the pin count if you do not require certain functionality. The pin count reductions that can be achieved by removing functionality are described under the headings:
•Dynamic and static memory and TIC
•Dynamic and static memory on page 10-6
•Dynamic memory and TIC on page 10-6
•Static memory and TIC on page 10-7
•Dynamic memory on page 10-7
•Static memory on page 10-8.
Note
•The signals that are normally multiplexed or not taken off chip are not counted in the following tables. The signals are MPMCRPVHHOUT,
MPMCTESTREQA, and MPMCTESTREQB.
•The output and feedback clocks are not counted on the table as various clocking strategies can be used.
10.3.1Dynamic and static memory and TIC
Table 10-3 shows the pin counts that can be achieved for 32-bit and 16-bit systems containing dynamic and static memory and a TIC.
Table 10-3 Pin counts for system with dynamic and static memory and TIC
Databus |
Control |
Address |
Total |
|
|
|
|
16 |
26 |
28 |
70 |
|
|
|
|
32 |
26 |
28 |
86 |
|
|
|
|
ARM DDI 0215A |
Copyright © 2002 ARM Limited. All rights reserved. |
10-5 |
Off-chip Connectivity
10.3.2Dynamic and static memory
Table 10-4 shows the pin counts that can be achieved for 32-bit and 16-bit systems containing dynamic and static memory.
Table 10-4 Pin counts for system with dynamic and static memory
Databus |
Control |
Address |
Total |
|
|
|
|
16 |
25 |
28 |
69 |
|
|
|
|
32 |
25 |
28 |
85 |
|
|
|
|
The MPMCTESTIN signals are not required.
10.3.3Dynamic memory and TIC
Table 10-5 shows the pin counts that can be achieved for 32-bit and 16-bit systems containing dynamic memory and TIC.
Table 10-5 Pin counts for system with dynamic memory and TIC
Databus |
Control |
Address |
Total |
|
|
|
|
16 |
16 |
15 |
47 |
|
|
|
|
32 |
16 |
15 |
63 |
|
|
|
|
The MPMCADDROUT[27:15] address signals are not required.
The following static memory signals are not required:
•nMPMPMCSTCSOUT[3:0]
•nMPMCOEOUT
•nMPMCBLSOUT[3:0]
•nMPMCWEOUT.
10-6 |
Copyright © 2002 ARM Limited. All rights reserved. |
ARM DDI 0215A |
Off-chip Connectivity
10.3.4Static memory and TIC
Table 10-6 shows the pin counts that can be achieved for 32-bit and 16-bit systems containing static memory and a TIC.
Table 10-6 Pin counts for system with static memory and TIC
Databus |
Control |
Address |
Total |
|
|
|
|
16 |
11 |
28 |
55 |
|
|
|
|
32 |
11 |
28 |
71 |
|
|
|
|
The following dynamic memory signals are not required:
•nMPMCDYCSOUT[3:0]
•MPMCCKEOUT[3:0]
•nMPMCRASOUT
•nMPMCCASOUT
•nMPMCRPOUT
•MPMCDQMOUT[3:0].
10.3.5Dynamic memory
Table 10-7 shows the pin counts that can be achieved for 32-bit and 16-bit systems containing dynamic memory.
Table 10-7 Pin counts for system with dynamic memory
Databus |
Control |
Address |
Total |
|
|
|
|
16 |
15 |
15 |
46 |
|
|
|
|
32 |
15 |
15 |
62 |
|
|
|
|
The MPMCADDROUT[27:15] address signals are not required.
The following static memory signals are not required:
•nMPMPMCSTCSOUT[3:0]
•nMPMCOEOUT
•nMPMCBLSOUT[3:0]
•nMPMCWEOUT.
The MPMCTESTIN test signal is not required.
ARM DDI 0215A |
Copyright © 2002 ARM Limited. All rights reserved. |
10-7 |
Off-chip Connectivity
10.3.6Static memory
Table 10-8 shows the pin counts that can be achieved for 32-bit and 16-bit systems containing static memory.
Table 10-8 Pin counts for system with static memory
Databus |
Control |
Address |
Total |
|
|
|
|
16 |
13 |
28 |
57 |
|
|
|
|
32 |
13 |
28 |
73 |
|
|
|
|
The following dynamic memory signals are not required:
•nMPMCDYCSOUT[3:0]
•MPMCCKEOUT[3:0]
•nMPMCRASOUT
•nMPMCCASOUT
•nMPMCRPOUT.
The MPMCTESTIN test signals are not required.
10-8 |
Copyright © 2002 ARM Limited. All rights reserved. |
ARM DDI 0215A |