List of Tables

Change history ..............................................................................................................

ii

Table 2-1

Memory bank selection ...........................................................................................

2-15

Table 3-1

PrimeCell MPMC register summary ..........................................................................

3-2

Table 3-2

MPMCControl register ...............................................................................................

3-8

Table 3-3

MPMCStatus register ..............................................................................................

3-11

Table 3-4

MPMCConfig register ..............................................................................................

3-11

Table 3-5

MPMCDynamicControl register ...............................................................................

3-13

Table 3-6

Output voltage settings ...........................................................................................

3-15

Table 3-7

MPMCDynamicRefresh register ..............................................................................

3-15

Table 3-8

MPMCDynamictRP register ....................................................................................

3-16

Table 3-9

MPMCDynamictRAS register ..................................................................................

3-17

Table 3-10

MPMCDynamictSREX register ...............................................................................

3-17

Table 3-11

MPMCDynamictAPR register ..................................................................................

3-18

Table 3-12

MPMCDynamictDAL register ..................................................................................

3-18

Table 3-13

MPMCDynamictWR register ...................................................................................

3-19

Table 3-14

MPMCDynamictRC register ....................................................................................

3-19

Table 3-15

MPMCDynamictRFC register ..................................................................................

3-20

Table 3-16

MPMCDynamictXSR register ..................................................................................

3-20

Table 3-17

MPMCDynamictRRD register ..................................................................................

3-21

Table 3-18

MPMCDynamictMRD register .................................................................................

3-21

Table 3-19

MPMCStaticExtendedWait register .........................................................................

3-22

ARM DDI 0215A

Copyright © 2002 ARM Limited. All rights reserved.

vii

Table 3-20

MPMCDynamicConfig[0,1,2,3] register ..................................................................

3-22

Table 3-21

Address mapping ....................................................................................................

3-24

Table 3-22

MPMCDynamicRasCas[0,1,2,3] register ................................................................

3-27

Table 3-23

MPMCStaticConfig[0,1,2,3] register .......................................................................

3-27

Table 3-24

MPMCStaticWaitWen[0,1,2,3] register ...................................................................

3-30

Table 3-25

MPMCStaticWaitOen[0,1,2,3] register ....................................................................

3-31

Table 3-26

MPMCStaticWaitRd[0,1,2,3] register ......................................................................

3-31

Table 3-27

MPMCStaticWaitPage[0,1,2,3] register ..................................................................

3-32

Table 3-28

MPMCStaticWaitWr[0,1,2,3] register ......................................................................

3-33

Table 3-29

MPMCStaticWaitTurn[0,1,2,3] register ...................................................................

3-33

Table 3-30

Conceptual MPMC Additional Peripheral ID register ..............................................

3-34

Table 3-31

MPMCPeriphID4 register ........................................................................................

3-34

Table 3-32

MPMCPeriphID5-7 registers ...................................................................................

3-35

Table 3-33

Conceptual MPMC Peripheral ID register ...............................................................

3-35

Table 3-34

MPMCPeriphID0 register ........................................................................................

3-36

Table 3-35

MPMCPeriphID1 register ........................................................................................

3-37

Table 3-36

MPMCPeriphID2 register ........................................................................................

3-37

Table 3-37

MPMCPeriphID3 register ........................................................................................

3-38

Table 3-38

Conceptual PrimeCell ID register ...........................................................................

3-39

Table 4-1

Test registers memory map ......................................................................................

4-4

Table 4-2

MPMCITCR register .................................................................................................

4-4

Table 4-3

MPMCITIP register ...................................................................................................

4-5

Table 4-4

MPMCITOP register .................................................................................................

4-7

Table 5-1

Static memory controller configurations ....................................................................

5-2

Table 5-2

MPMCDATAOUT[31:0] controlled by nMPMCDATAOUTEN[3:0] ..........................

5-27

Table 5-3

Little-endian read, 8-bit external bus ......................................................................

5-28

Table 5-4

Little-endian read, 16-bit external bus ....................................................................

5-29

Table 5-5

Little-endian read, 32-bit external bus ....................................................................

5-29

Table 5-6

Little-endian write, 8-bit external bus ......................................................................

5-30

Table 5-7

Little-endian write, 16-bit external bus ....................................................................

5-30

Table 5-8

Little-endian write, 32-bit external bus ....................................................................

5-31

Table 5-9

Big-endian read, 8-bit external bus .........................................................................

5-32

Table 5-10

Big-endian read, 16-bit external bus .......................................................................

5-32

Table 5-11

Big-endian read, 32-bit external bus .......................................................................

5-33

Table 5-12

Big-endian write, 8-bit external bus ........................................................................

5-34

Table 5-13

Big-endian write, 16-bit external bus ......................................................................

5-34

Table 5-14

Big-endian write, 32-bit external bus ......................................................................

5-35

Table 6-1

Address mapping for 16M SDRAM (1Mx16, RBC) ...................................................

6-6

Table 6-2

Address mapping for 16M SDRAM (2Mx8, RBC) .....................................................

6-7

Table 6-3

Address mapping for 64M SDRAM (2Mx32, RBC) ...................................................

6-8

Table 6-4

Address mapping for 64M SDRAM 4Mx16, RBC) ....................................................

6-9

Table 6-5

Address mapping for 64M SDRAM (8Mx8, RBC) ...................................................

6-10

Table 6-6

Address mapping for 128M SDRAM (4Mx32, RBC) ...............................................

6-11

Table 6-7

Address mapping for 128M SDRAM (8Mx16, RBC) ...............................................

6-12

Table 6-8

Address mapping for 128M SDRAM (16Mx8, RBC) ...............................................

6-13

Table 6-9

Address mapping for 128M SDRAM (8Mx32, RBC) ...............................................

6-14

Table 6-10

Address mapping for 128M SDRAM (16Mx16, RBC) .............................................

6-15

viii

Copyright © 2002 ARM Limited. All rights reserved.

ARM DDI 0215A

List of Tables

Table 6-11

Address mapping for 256M SDRAM (32Mx8, RBC) ...............................................

6-16

Table 6-12

Address mapping for 256M SDRAM (32Mx16, RBC) .............................................

6-17

Table 6-13

Address mapping for 256M SDRAM (64Mx8, RBC) ...............................................

6-18

Table 6-14

Address mapping for 16M SDRAM (1Mx16, BRC) .................................................

6-20

Table 6-15

Address mapping for 16M SDRAM (2Mx8, BRC) ...................................................

6-21

Table 6-16

Address mapping for 64M SDRAM (2Mx32, BRC) .................................................

6-22

Table 6-17

Address mapping for 64M SDRAM (4Mx16, BRC) .................................................

6-23

Table 6-18

Address mapping for 64M SDRAM (8Mx8, BRC) ...................................................

6-24

Table 6-19

Address mapping for 128M SDRAM (4Mx32, BRC) ...............................................

6-25

Table 6-20

Address mapping for 128M SDRAM (8Mx16, BRC) ...............................................

6-26

Table 6-21

Address mapping for 128M SDRAM (16Mx8, BRC) ...............................................

6-27

Table 6-22

Address mapping for 256M SDRAM (8Mx32, BRC) ...............................................

6-28

Table 6-23

Address mapping for 256M SDRAM (16Mx16, BRC) .............................................

6-29

Table 6-24

Address mapping for 256M SDRAM (32Mx8, BRC) ...............................................

6-30

Table 6-25

Address mapping for 512M SDRAM (32Mx16, BRC) .............................................

6-31

Table 6-26

Address mapping for 512M SDRAM (64Mx8, BRC) ...............................................

6-32

Table 6-27

Address mapping for 16M SDRAM (1Mx16, RBC) .................................................

6-33

Table 6-28

Address mapping for 16M SDRAM (2Mx8, RBC) ...................................................

6-34

Table 6-29

Address mapping for 64M SDRAM (4Mx16, RBC) .................................................

6-35

Table 6-30

Address mapping for 64M SDRAM (8Mx8, RBC) ...................................................

6-36

Table 6-31

Address mapping for 128M SDRAM (8Mx16, RBC) ...............................................

6-37

Table 6-32

Address mapping for 128M SDRAM (16Mx8, RBC) ...............................................

6-38

Table 6-33

Address mapping for 256M SDRAM (16Mx16, RBC) .............................................

6-39

Table 6-34

Address mapping for 256M SDRAM (32Mx8, RBC) ...............................................

6-40

Table 6-35

Address mapping for 512M SDRAM (32Mx16, RBC) .............................................

6-41

Table 6-36

Address mapping for 512M SDRAM (64Mx8, RBC) ...............................................

6-42

Table 6-37

Address mapping for 16M SDRAM (1Mx16, BRC) .................................................

6-43

Table 6-38

Address mapping for 16M SDRAM (2Mx8, BRC) ...................................................

6-44

Table 6-39

Address mapping for 64M SDRAM (4Mx16, BRC) .................................................

6-45

Table 6-40

Address mapping for 64M SDRAM (8Mx8, BRC) ...................................................

6-46

Table 6-41

Address mapping for 128M SDRAM (8Mx16, BRC) ...............................................

6-47

Table 6-42

Address mapping for 128M SDRAM (16Mx8, BRC) ...............................................

6-48

Table 6-43

Address mapping for 256M SDRAM (16Mx16, BRC) .............................................

6-49

Table 6-44

Address mapping for 256M SDRAM (32Mx8, BRC) ...............................................

6-50

Table 6-45

Address mapping for 512M SDRAM (32Mx16, BRC) .............................................

6-51

Table 6-46

Address mapping for 512M SDRAM (64Mx8, BRC) ...............................................

6-52

Table 6-47

Synchronous memory commands used by MPMC .................................................

6-53

Table 6-48

Synchronous memory commands programmed by software ..................................

6-53

Table 6-49

Required MPMC SDRAM mode register settings ...................................................

6-55

Table 6-50

Field settings for Micron MT48LC4M16A2 SDRAM ................................................

6-56

Table 6-51

Required Micron SDRAM mode register settings ....................................................

6-57

Table 6-52

Field settings for low-power SDRAM ......................................................................

6-59

Table 6-53

SDRAM mode register settings for low-power SDRAM ..........................................

6-60

Table 6-54

Required low-power SDRAM extended mode register settings ..............................

6-61

Table 6-55

Field settings for Micron MT28S4M16LC SyncFlash ..............................................

6-62

Table 6-56

SDRAM mode register settings for Micron SyncFlash SDRAM ..............................

6-63

Table 6-57

SyncFlash commands .............................................................................................

6-64

ARM DDI 0215A

Copyright © 2002 ARM Limited. All rights reserved.

ix

Table 7-1

Buffer access latency ................................................................................................

7-4

Table 10-1

External pins ...........................................................................................................

10-2

Table 10-2

Multiplexed pins ......................................................................................................

10-3

Table 10-3

Pin counts for system with dynamic and static memory and TIC ...........................

10-5

Table 10-4

Pin counts for system with dynamic and static memory .........................................

10-6

Table 10-5

Pin counts for system with dynamic memory and TIC ............................................

10-6

Table 10-6

Pin counts for system with static memory and TIC .................................................

10-7

Table 10-7

Pin counts for system with dynamic memory ..........................................................

10-7

Table 10-8

Pin counts for system with static memory ...............................................................

10-8

Table 10-9

Clock frequencies .................................................................................................

10-18

Table B-1

Troubleshooting .......................................................................................................

. B-2

Table C-1

AHB register signal descriptions ...............................................................................

C-2

Table C-2

AHB memory signal descriptions ..............................................................................

C-4

Table C-3

Miscellaneous and clock signal descriptions ............................................................

C-6

Table C-4

Pad interface and control signal descriptions ...........................................................

C-8

Table C-5

TIC signal descriptions ...........................................................................................

C-12

Table C-6

Scan test signal descriptions ..................................................................................

C-14

x

Copyright © 2002 ARM Limited. All rights reserved.

ARM DDI 0215A