Chapter 8

Test Interface Controller

This chapter describes the Test Interface Controller (TIC). It contains the following sections:

•About TIC on page 8-2

•Sequence of events leading to entry into TIC test mode on page 8-3.

Test Interface Controller

8.1About TIC

The TIC converts externally applied test vectors into internal transfers on the TIC AHB bus. A three-wire external handshake protocol is used, with two inputs, MPMCTESTREQA and MPMCTESTREQB, controlling the type of vector that is applied and a single output, MPMCTESTACK, that indicates when the next vector can be applied. The MPMCTESTIN input is used to indicate that TIC test mode must be entered. Typically, the TIC is the highest priority AMBA bus master, ensuring test access under all conditions. TIC testing requires a 32-bit databus. Therefore, if TIC test support is required for systems with a 16-bit MPMCDATA databus then the upper 16 bits of the databus, MPMCDATA[31:16], must be multiplexed onto other pads during test mode.

Test Interface Controller

8.2Sequence of events leading to entry into TIC test mode

The following description assumes that, within a typical system, the processor is always requesting access to the external bus, but the TIC has the highest priority to bus access. A typical sequence of events in using the TIC to apply test patterns is:

1.Apply reset asynchronously.

2.Assert the MPMCTESTIN test input to enter test mode.

3.When the reset is removed asynchronously, the MPMC enters TIC test mode.

4.The TIC block asserts its HBUSREQTIC signal to the arbiter, requesting access to the AHB bus. Because the TIC is the highest priority, HGRANTTIC is asserted and the granted TIC takes ownership of the AHB bus.

For further information on TIC testing see the AHB Example AMBA System Technical Reference Manual.

Note

The MPMCTESTIN signal is usually fed to the clock generation logic so that HCLK can be switched to test speed.

Test Interface Controller