Off-chip Connectivity

10.4Address pin reduction

Depending on the size of the memory parts, not all the address pins have to be bonded out.

Off-chip Connectivity

10.5Chip select pin reduction

Depending on the number of memory chip selects required, not all of the chips selects have to bonded out.

Off-chip Connectivity

10.6Device support

If the Micron SyncFlash devices are not required to be supported the nMPMCRPOUT pin is not required.

Off-chip Connectivity

10.7Multiplexing static and dynamic memory pins

SDRAM memories use a multiplexed address. These devices use up to 15 address pins.

Static memories do not perform address multiplexing and so require more address pins.

For systems where the SDRAM memory chip selects databus is wider than the static memory chip selects databus. The upper static memory address bits can be multiplexed with the upper bits of the SDRAM databus to reduce the pin count.

For example, in a system where the static memory devices use a 16-bit databus and 24 address pins, and the SDRAM memory devices use a 32-bit databus and 15 address pins. The static memory controller uses more address pins than the dynamic memory controller, the dynamic memory controller uses more data pins than the static memory controller. As only one transaction can be active at a time. It is possible to multiplex the top 8-bits of the SDRAM data pins with the top 8-bits of the static memory address pins. This can be performed by ORing the relevant MPMCADDROUT and MPMCDATAOUT signals externally.

Note

If the above optimization is to be performed then appropriate testing is required. This ensures that the pads are driven in the correct direction for static and dynamic memory accesses.