Добавил:

Andrey Опубликованный материал нарушает ваши авторские права? Сообщите нам.

Вуз:

Санкт-Петербургский государственный электротехнический университет "ЛЭТИ"

Предмет:

Электротехника

Файл:

ARM PrimeCell multiport memory controller technical reference manual.pdf

Скачиваний:

Добавлен:

23.08.2013

Размер:

1.79 Mб

Скачать

☆

<<< < Предыдущая 1 2 3 4 5 6 7 8 9 1011 / 3611 12 13 14 15 16 17 18 19 20 21 22 23 24 25 > Следующая >>>

Chapter 3

Programmer’s Model

This chapter describes the ARM PrimeCell MPMC (PL172) registers and provides details required when programming the microcontroller. It contains the following sections:

•About the programmer’s model on page 3-2

•Register descriptions on page 3-7.

ARM DDI 0215A

3-1

Programmer’s Model

3.1About the programmer’s model

The base address of the PrimeCell MPMC is not fixed, and can be different for any particular system implementation. However, the offset of any particular register from the base address is fixed. The registers of the PrimeCell MPMC are selected by the

HSELMPMCREG signal.

The external memory addresses are not fixed and can be different for any particular system implementation. Transfers to the external memories of the PrimeCell MPMC are selected by the HSELMPMC[3:0]CS[7:0] signals.

Note

[3:0] indicates the AHB port number, and [7:0] indicates the chip select to be accessed.

The PrimeCell MPMC registers are shown in Table 3-1.

Table 3-1 PrimeCell MPMC register summary

	Offset			Reset	Reset
Register	from	Type	Width	Reset	Reset	Description
Register	from	Type	Width	HRESETn	nPOR	Description
	base			HRESETn	nPOR
	base

MPMCControl	0x000	Read/write	4	0x1	0x3	Control register

MPMCStatus	0x004	Read	3	-	0x0	Status register

MPMCConfig	0x008	Read/write	2	-	0x000	Configuration register

MPMCDynamicControl	0x020	Read/write	8	-	0x002	Dynamic memory control
						register

MPMCDynamicRefresh	0x024	Read/write	11	-	0x0	Dynamic memory refresh
						timer

MPMCDynamictRP	0x030	Read/write	4	-	0x0F	Dynamic memory precharge
						command period (tRP)

MPMCDynamictRAS	0x034	Read/write	4	-	0xF	Dynamic memory active to
						precharge command period
						(tRAS)

MPMCDynamictSREX	0x038	Read/write	4	-	0xF	Dynamic memory self-refresh
						exit time (tSREX)

MPMCDynamictAPR	0x03C	Read/write	4	-	0xF	Dynamic memory last data out
						to active time (tAPR)

3-2

ARM DDI 0215A

						Programmer’s Model
			Table 3-1 PrimeCell MPMC register summary (continued)

	Offset			Reset	Reset
Register	from	Type	Width	Reset	Reset	Description
Register	from	Type	Width	HRESETn	nPOR	Description
	base			HRESETn	nPOR
	base

MPMCDynamictDAL	0x040	Read/write	4	-	0xF	Dynamic memory data-in to
						active command time (tDAL or
						tAPW)
MPMCDynamictWR	0x044	Read/write	4	-	0xF	Dynamic memory write
						recovery time (tWR, or tDPL, or
						tRWL, or tRDL)
MPMCDynamictRC	0x048	Read/write	5	-	0x1F	Dynamic memory active to
						active command period (tRC)

MPMCDynamictRFC	0x04C	Read/write	5	-	0x1F	Dynamic memory auto refresh
						period, and auto refresh to
						active command period (tRFC)

MPMCDynamictXSR	0x050	Read/write	5	-	0x1F	Dynamic memory exit
						self-refresh to active command
						time (tXSR)

MPMCDynamictRRD	0x054	Read/write	4	-	0xF	Dynamic memory active bank
						A to active B time (tRRD)

MPMCDynamictMRD	0x058	Read/write	4	-	0xF	Dynamic memory load mode
						register to active command
						time (tMRD)

MPMCStaticExtendedWait	0x080	Read/write	10	-	0x0	Static memory extended wait

MPMCDynamicConfig0	0x100	Read/write	17	-	0x0	Dynamic memory
						configuration register

MPMCDynamicRasCas0	0x104	Read/write	4	-	0x303	Dynamic memory RAS and
						CAS delay

MPMCDynamicConfig1	0x120	Read/write	17	-	0x0	Dynamic memory
						configuration register

MPMCDynamicRasCas1	0x124	Read/write	4	-	0x303	Dynamic memory RAS and
						CAS delay

MPMCDynamicConfig2	0x140	Read/write	17	-	0x0	Dynamic memory
						configuration register

ARM DDI 0215A

3-3

Programmer’s Model

Table 3-1 PrimeCell MPMC register summary (continued)

	Offset			Reset	Reset
Register	from	Type	Width	Reset	Reset	Description
Register	from	Type	Width	HRESETn	nPOR	Description
	base			HRESETn	nPOR
	base

MPMCDynamicRasCas2	0x144	Read/write	4	-	0x303	Dynamic memory RAS and
						CAS delay

MPMCDynamicConfig3	0x160	Read/write	17	-	0x0	Dynamic memory
						configuration register

MPMCDynamicRasCas3	0x164	Read/write	4	-	0x303	Dynamic memory RAS and
						CAS delay

MPMCStaticConfig0	0x200	Read/write	8	-	0x0	Static memory configuration
						register

MPMCStaticWaitWen0	0x204	Read/write	4	-	0x0	Static memory write enable
						delay

MPMCStaticWaitOen0	0x208	Read/write	4	-	0x0	Static memory output enable
						delay

MPMCStaticWaitRd0	0x20C	Read/write	5	-	0x1F	Static memory read delay

MPMCStaticWaitPage0	0x210	Read/write	5	-	0x1F	Static memory page mode read
						delay

MPMCStaticWaitWr0	0x214	Read/write	5	-	0x1F	Static memory write delay

MPMCStaticWaitTurn0	0x218	Read/write	4	-	0xF	Static memory turn round
						delay

MPMCStaticConfig1	0x220	Read/write	8	-	0x0	Static memory configuration
						register

MPMCStaticWaitWen1	0x224	Read/write	4	-	0x0	Static memory write enable
						delay

MPMCStaticWaitOen1	0x228	Read/write	4	-	0x0	Static memory output enable
						delay

MPMCStaticWaitRd1	0x22C	Read/write	5	-	0x1F	Static memory read delay

MPMCStaticWaitPage1	0x230	Read/write	5	-	0x1F	Static memory page mode read
						delay

MPMCStaticWaitWr1	0x234	Read/write	5	-	0x1F	Static memory write delay

3-4

ARM DDI 0215A

						Programmer’s Model
			Table 3-1 PrimeCell MPMC register summary (continued)

	Offset			Reset	Reset
Register	from	Type	Width	Reset	Reset	Description
Register	from	Type	Width	HRESETn	nPOR	Description
	base			HRESETn	nPOR
	base

MPMCStaticWaitTurn1	0x238	Read/write	4	-	0xF	Static memory turn round
						delay

MPMCStaticConfig2	0x240	Read/write	8	-	0x0	Static memory configuration
						register

MPMCStaticWaitWen2	0x244	Read/write	4	-	0x0	Static memory write enable
						delay

MPMCStaticWaitOen2	0x248	Read/write	4	-	0x0	Static memory output enable
						delay

MPMCStaticWaitRd2	0x24C	Read/write	5	-	0x1F	Static memory read delay

MPMCStaticWaitPage2	0x250	Read/write	5	-	0x1F	Static memory page mode read
						delay

MPMCStaticWaitWr2	0x254	Read/write	5	-	0x1F	Static memory write delay

MPMCStaticWaitTurn2	0x258	Read/write	4	-	0xF	Static memory turn round
						delay

MPMCStaticConfig3	0x260	Read/write	8	-	0x0	Static memory configuration
						register

MPMCStaticWaitWen3	0x264	Read/write	4	-	0x0	Static memory write enable
						delay

MPMCStaticWaitOen3	0x268	Read/write	4	-	0x0	Static memory output enable
						delay

MPMCStaticWaitRd3	0x26C	Read/write	5	-	0x1F	Static memory read delay

MPMCStaticWaitPage3	0x270	Read/write	5	-	0x1F	Static memory page mode read
						delay

MPMCStaticWaitWr3	0x274	Read/write	5	-	0x1F	Static memory write delay

MPMCStaticWaitTurn3	0x278	Read/write	4	-	0xF	Static memory turn round
						delay

MPMCITCR	0xF00	Read/write	1	0x0	0x0	Test control register

MPMCITIP	0xF20	Read/write	8	-	-	Test input register

MPMCITOP	0xF40	Read/write	2	-	-	Test output register

ARM DDI 0215A

3-5

Programmer’s Model

Table 3-1 PrimeCell MPMC register summary (continued)

	Offset			Reset	Reset
Register	from	Type	Width	Reset	Reset	Description
Register	from	Type	Width	HRESETn	nPOR	Description
	base			HRESETn	nPOR
	base

MPMCPeriphID4	0xFD0	Read	8	0x1	0x1	Peripheral identification
						register bits [39:32]

MPMCPeriphID5	0xFD4	Read	8	0x0	0x0	Reserved for peripheral
						identification register

MPMCPeriphID6	0xFD8	Read	8	0x0	0x0	Reserved for peripheral
						identification register

MPMCPeriphID7	0xFDC	Read	8	0x0	0x0	Reserved for peripheral
						identification register

MPMCPeriphID0	0xFE0	Read	8	0x72	0x72	Peripheral identification
						register bits [7:0]

MPMCPeriphID1	0xFE4	Read	8	0x11	0x11	Peripheral identification
						register bits [15:8]

MPMCPeriphID2	0xFE8	Read	8	0x04	0x04a	Peripheral identification
						register bits [23:16]

MPMCPeriphID3	0xFEC	Read	8	0xC2	0xC2	Peripheral identification
						register bits [31:24]

MPMCPCellID0	0xFFO	Read	8	0x0D	0x0D	PrimeCell identification
						register bits [7:0]

MPMCPCellID1	0xFF4	Read	8	0xF0	0xF0	PrimeCell identification
						register bits [15:8]

MPMCPCellID2	0xFF8	Read	8	0x05	0x05	PrimeCell identification
						register bits [23:16]

MPMCPCellID3	0xFFC	Read	8	0xB1	0xB1	PrimeCell identification
						register bits [31:24]

a. Revision dependent

3-6

ARM DDI 0215A

<<< < Предыдущая 1 2 3 4 5 6 7 8 9 1011 / 3611 12 13 14 15 16 17 18 19 20 21 22 23 24 25 > Следующая >>>

Соседние файлы в предмете Электротехника

#
23.08.2013377.02 Кб15ARM PrimeCell DC-DC converter interface technical reference manual.pdf
#
23.08.20131.2 Mб14ARM PrimeCell DMA controller technical reference manual.pdf
#
23.08.2013487.36 Кб10ARM PrimeCell generic infrared interface technical reference manual.pdf
#
23.08.2013744 Кб19ARM PrimeCell GPIO technical reference manual.pdf
#
23.08.2013644.37 Кб12ARM PrimeCell multimedia card interface ARM PrimeCell static memory controller technical reference manual.pdf
#
23.08.20131.79 Mб20ARM PrimeCell multiport memory controller technical reference manual.pdf
#
23.08.2013375.85 Кб14ARM PrimeCell PS-2 interface technical reference manual.pdf
#
23.08.2013641.47 Кб12ARM PrimeCell RTC technical reference manual.pdf
#
23.08.2013576.81 Кб14ARM PrimeCell SDRAM controller technical reference manual.pdf
#
23.08.20131.11 Mб15ARM PrimeCell single master DMA controller technical reference manual.pdf
#
23.08.20131.21 Mб17ARM PrimeCell smart card interface technical reference manual.pdf