Chapter 1

Introduction

This chapter introduces the ARM PrimeCell MultiPort Memory Controller (PL172). It contains the following sections:

•About the ARM PrimeCell MultiPort Memory Controller (PL172) on page 1-2

•Supported dynamic memory devices on page 1-4

•Supported static memory devices on page 1-6.

Introduction

1.1About the ARM PrimeCell MultiPort Memory Controller (PL172)

The PrimeCell MultiPort Memory Controller (MPMC) is an Advanced Microcontroller Bus Architecture (AMBA Rev 2.0) compliant System-on-Chip (SoC) peripheral that is developed, tested, and licensed by ARM Limited. It connects to the Advanced High-performance Bus (AHB).

1.1.1Features of the PrimeCell MPMC

The PrimeCell MPMC offers:

•AMBA 32-bit AHB compliancy.

•Dynamic memory interface support including SDRAM, JEDEC low-power SDRAM, and Micron SyncFlash.

•Asynchronous static memory device support including RAM, ROM, and Flash, with or without asynchronous page mode.

•Software support for 8 and 16 bit NAND flash.

•Designed to operate with cached processors with write through (ARM7x), or copy back (ARM9x, ARM10x) caches.

•Designed to operate with uncached, and tightly coupled memory processors.

•Low transaction latency.

•Read and write buffers to reduce latency and to improve performance, particularly for uncached processors.

•Four AHB interfaces for accessing external memory.

•8-bit, 16-bit, and 32-bit wide static memory support.

•16-bit and 32-bit wide synchronous SDRAM and Micron SyncFlash memory support.

•Static memory features include:

—asynchronous page mode read

—programmable wait states

—bus turnaround delay

—output enable, and write enable delays

—extended wait.

Introduction

•Four chip selects for synchronous memory and four chip selects for static memory devices.

•Software controllable HCLK to MPMCCLKOUT ratio.

•Power-saving modes dynamically control SDRAM MPMCCKEOUT and

MPMCCLKOUT.

•Dynamic memory self-refresh mode supported by a Power Management Unit (PMU) interface or by software.

•Controller supports 2K, 4K, and 8K row address synchronous memory parts. That is typical 512MB, 256MB, 128MB, and 16Mb parts, with 8, 16, or 32 DQ bits per device.

•Two reset domains enable dynamic memory contents to be preserved over a soft reset.

•A separate AHB interface to program the MPMC. This enables the PrimeCell MPMC registers to be situated in memory with other system peripheral registers.

•Locked AHB transactions supported.

•Support for AHB burst types.

•Little and big-endian support.

•Test Interface Controller (TIC) support.

•PrimeCell ID support.

Note

Synchronous static memory devices (synchronous burst mode) are not supported.

Introduction

1.2Supported dynamic memory devices

This section provides examples of dynamic memory devices that are supported by the PrimeCell MPMC:

•SDRAM devices

•Synchronous Flash devices on page 1-5

•JEDEC low-power SDRAM devices on page 1-5.

Note

This is not an exhaustive list of supported devices.

1.2.1SDRAM devices

The PrimeCell MPMC supports the following SDRAM devices:

•16Mb devices:

—Micron MT48LC1M16A1S

—Samsung K4S160822D-G/F

—Samsung K4S641632C.

•64Mb devices:

—Micron MT48LC2M32B2-6

—Micron MT28S4M162C-10

—Elphida VDP4564323-10

—Hitachi HM5264805F-75.

•128Mb devices:

—Micron MT48LC4M32B2

—Micron MT48LC16M8A2

—Micron MT48LC8M16A2

•256Mb devices:

—Elphida VPP45256163-10

—Micron MT48LC16M16A2-8E

—Hitachi HM522532F-B6

—Hitachi HM5225805B-75.

•512Mb device:

—Elphida HM5257805B-A6.

Introduction

1.2.2Synchronous Flash devices

The PrimeCell MPMC supports the following 64Mb devices:

•Micron MT28S4M16LC-10

•Micron MT28S4M16LC-12

1.2.3JEDEC low-power SDRAM devices

The PrimeCell MPMC supports the following JEDEC low-power SDRAM devices:

•64Mb Micron MT48LC2M32LFFC-8

•128Mb Infineon HYB25L128160AC.