Chapter 9

System Connectivity

This chapter describes the system connectivity aspects relating to the MPMC. It contains the following sections:

•On-chip signals on page 9-2

•Self-refresh entry on page 9-6

•Example system on page 9-10

System Connectivity

9.1On-chip signals

The on-chip signals are described in the following sections:

•AHB register interface connectivity

•AHB memory interface connectivity on page 9-4

•TIC test connectivity on page 9-4

•Reset controller connectivity on page 9-4

•Power management connectivity on page 9-5.

9.1.1AHB register interface connectivity

The AHB register interface must be connected to the AHB bus with the microprocessor so that the microprocessor can program the MPMC.

Figure 9-1 on page 9-3 shows the MPMC system interconnection diagram.

System Connectivity

9.1.2AHB memory interface connectivity

AHB memory interface 0 is the highest priority interface and is normally connected to the AHB bus with high-bandwidth, low-latency AHB masters. AHB memory interface 1 is the next highest priority interface. Priorities having greater numbers are lower priority. The lowest priority is system-dependent. Any unused AHB interfaces must have their AHB input signals tied LOW.

9.1.3TIC test connectivity

The TIC AHB master interface, if required, must be connected to the same bus as the microprocessor. The TIC controller must be the highest priority master on this bus. The MPMCTESTIN signal must be asserted during reset to enter TIC test mode. The MPMCTESTIN signal must also be sent to the clock generation logic so that the appropriate test clock is selected.

Note

•The TIC controller must not be the default master. Because the TIC master only operates at test speed, it might not function correctly if granted the bus at functional speed.

•The TIC must be granted the bus in test mode. This is normally performed by making the TIC the highest priority master on the AHB bus.

9.1.4Reset controller connectivity

The power-on reset signal from the reset controller must be connected to the MPMC nPOR signal. If the reset controller does not generate a power-on reset signal then the HRESETn signal must be connected to nPOR. However, in this situation the following functionality is seen:

•On HRESETn (and nPOR) reset the complete memory controller is reset. All memory controller state machines are reset. The memory controller must therefore be reinitalized after HRESETn (and nPOR) goes inactive.

•It might not be possible for the system to be re-awakened from self-refresh mode using HRESETn (and nPOR) without data being lost in the SDRAM memory. This is because all statemachines are reset in the memory controller and it might not be possible to restart the SDRAM auto-refresh commands before the contents of the SDRAM are corrupted.

System Connectivity

9.1.5Power management connectivity

The power management units self-refresh signals must be connected to the MPMC

MPMCSREFREQ and MPMCSREFACK signals. When MPMCSREFREQ is asserted, the controller closes any open memory banks, flushes the buffers, and then puts the memory into self-refresh mode. The MPMCSREFACK signal is used to indicate to the PMU that the external memories are in self-refresh state. The system must ensure that the memory subsystem is idle before asserting MPMCSREFREQ. Deasserting MPMCSREFREQ returns the memory to normal operation. See the memory data sheet for refresh requirements.

If the PMU does not provide the required signals to automatically enter self-refresh mode, then the PrimeCell MPMC MPMCSREFREQ signal must be tied LOW. Self-refresh mode can instead be entered manually by programming the self-refresh bit (SR) in the MPMCDynamicControl register.