System Connectivity

9.2Self-refresh entry

The section describes:

•Power Management Unit self-refresh entry

•Manual self-refresh entry on page 9-7

•Forcing AHB masters idle on page 9-8.

Note

After self-refresh exit some devices require a number of auto-refresh cycles to take place. If this is the case the auto-refresh cycles must be generated by reprogramming the refresh period and waiting for the required number of refresh commands to occur.

9.2.1Power Management Unit self-refresh entry

Power Management Unit (PMU) self-refresh entry uses a PMU to handshake with the MPMC to enter self-refresh mode. These signals are shown in Figure 9-2.

MPMC

MPMCSREFREQ

MPMCSREFACK PMU

Figure 9-2 PMU self-refresh

When the PMU requires the SDRAM memory to enter self-refresh mode it must first ensure that there are no masters performing transactions to the MPMC. Various methodologies to perform this are described in Forcing AHB masters idle on page 9-8.

When the AHB masters cannot perform transfers to the MPMC the PMU can then assert the self-refresh request (MPMCSREFREQ) signal. The MPMC then flushes its buffers and puts the SDRAM memory into self-refresh mode. When the memory has been placed into self-refresh mode the MPMC asserts the self-refresh acknowledge (MPMCSREFACK) signal.

System Connectivity

The PMU can then gate HCLK as required, see *a in Figure 9-3.

For exit from self-refresh, the PMU re-enables the clocks, and then brings MPMCSREFREQ LOW. The SDRAM controller then exits self-refresh mode. When self-refresh is exited the memory controller does not allow any access to the SDRAM until the values in the MPMCDynamictSREX and MPMCDynamictXSR registers time out. When the SDRAM controller has exited self-refresh it lowers the MPMCSREFACK signal. The PMU can then enable the AHB masters to access the AHB bus. This can be performed in a number of ways:

•by performing soft reset

•by generating an interrupt

•by enabling a peripheral transfer to complete, which is used to stall the ARM processor

•by lowering the signal to the arbiter so that a dummy AHB master is no longer granted the bus.

*a

HCLK

MPMCSREFREQ

MPMCSREFACK

Figure 9-3 PMU self-refresh waveforms

9.2.2Manual self-refresh entry

Self-refresh can be entered manually in systems where the ARM processor can execute code from internal memory, or from another memory controller.

To enter self-refresh mode the processor must first ensure that there are no masters currently performing transactions to the MPMC. Various methodologies to perform this are described in Forcing AHB masters idle on page 9-8.

While the ARM processor is executing code from internal memory or another memory controller it must then set the SR bit (self-refresh request) in the MPMCDynamicControl register. The MPMC then flushes its buffers and put the memory into self-refresh mode. When the memory has been placed into self-refresh mode the MPMC asserts the SA bit (self-refresh acknowledge) in the MPMCStatus register. The ARM processor must wait until this bit goes active, before continuing the power down procedure. PMU to gate HCLK as necessary.

System Connectivity

For exit from self-refresh, the PMU re-enables the clocks and the ARM processor starts executing code. The ARM processor then clears the self-refresh request (SR) bit in the MPMCDynamicControl register. The SDRAM controller then proceeds to exit self-refresh mode, this takes about 200 clock cycles. When the SDRAM controller has exited self-refresh it clears the self-refresh acknowledge (SA) bit in the MPMCStatus register. The ARM processor can then reprogram the AHB masters to enable them to perform transactions to the MPMC.

9.2.3Forcing AHB masters idle

AHB masters can be forced idle by the following methods:

•The ARM processor can be used to program or interrupt the other masters to stop performing transfers. The ARM processor must then either enter a forever loop, or alternatively read a register in the PMU that waits the transfer until the processor has to re-awake.

•The PMU can assert a signal to the AHB arbiters which puts a dummy AHB master on the bus. For multi-layer AHB systems a MuxM2S component is required. Masters with AHB-Lite interfaces also require an AHB-Lite to AHB wrapper. See Figure 9-4 on page 9-9.

System Connectivity

Figure 9-4 Forcing AHB masters idle in a multi-layer system