8XC196Kx, Jx, CA USER’S MANUAL
COMPx_CON |
Address: |
x = 0, 1F88H |
(Continued) |
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x = 1, 1F8CH |
x = 0–1 |
Reset State: |
00H |
The EPA compare control (COMPx_CON) registers determine the function of the EPA compare channels.
7 |
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0 |
TB |
CE |
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M1 |
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M0 |
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RE |
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AD |
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ROT |
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RT |
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Number |
Mnemonic |
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2 |
AD |
A/D Conversion |
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Allows the EPA to start an A/D conversion that has been previously set |
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up in the A/D control registers. To use this feature, you must select the |
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EPA as the conversion source in the AD_CONTROL register. |
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1 |
= EPA compare event triggers an A/D conversion |
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0 |
= causes no A/D action |
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1 |
ROT |
Reset Opposite Timer and Reset Timer |
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These bits control whether an EPA compare event resets the reference |
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timer or the opposite timer. |
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ROT RT |
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X |
0 |
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reset function disabled |
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0 |
1 |
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resets reference timer |
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1 |
1 |
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resets opposite timer |
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The state of the TB bit (COMPx_CON.7) determines which timer is the |
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reference timer and which timer is the opposite timer. |
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0 |
RT |
Reset Timer |
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This bit controls whether the timer selected by the ROT bit will be reset |
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1 |
= resets the timer selected by the ROT bit |
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0 |
= disables the reset function |
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Figure 10-11. EPA Compare Control (COMPx_CON) Registers (Continued)
10.6 ENABLING THE EPA INTERRUPTS
The EPA generates four individual event interrupts, EPA0–EPA3, and the multiplexed event interrupt, EPAx. To enable the interrupts, set the corresponding bits in the INT_MASK register (Figure 5-5 on page 5-13). To enable the individual sources of the multiplexed EPAx interrupt, set the corresponding bits in the EPA_MASK (Figure 10-12) and EPA_MASK1(Figure 10-13) registers. (Chapter 5, “Standard and PTS Interrupts,” discusses the interrupts in greater detail.)
10-26
EVENT PROCESSOR ARRAY (EPA)
EPA_MASK |
Address: |
1FA0H |
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Reset State: |
0000H |
The EPA interrupt mask (EPA_MASK) register enables or disables (masks) interrupts associated with the multiplexed EPAx interrupt.
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15 |
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8 |
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CA, Jx |
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— |
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EPA8 |
EPA9 |
OVR0 |
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OVR1 |
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7 |
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0 |
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0VR2 |
OVR3 |
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OVR8 |
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OVR9 |
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15 |
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8 |
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Kx |
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EPA4 |
EPA5 |
EPA6 |
EPA7 |
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EPA8 |
EPA9 |
OVR0 |
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OVR1 |
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7 |
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OVR2 |
OVR3 |
OVR4 |
OVR5 |
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OVR6 |
OVR7 |
OVR8 |
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OVR9 |
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Bit |
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Function |
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Number |
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15:0† |
Setting a bit enables the corresponding interrupt as a multiplexed EPAx interrupt source. |
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The multiplexed EPAx interrupt is enabled by setting its interrupt enable bit in the interrupt |
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mask register (INT_MASK.0 = 1). |
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† Bits 2–5 and 12–15 are reserved on the 8XC196CA, Jx devices. For compatibility with future |
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devices, write zeros to these bits. |
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Figure 10-12. EPA Interrupt Mask (EPA_MASK) Register |
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EPA_MASK1 |
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Address: |
1FA4H |
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Reset State: |
00H |
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The EPA interrupt mask 1 (EPA_MASK1) register enables or disables (masks) interrupts associated with the EPAx interrupt.
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0 |
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COMP0 |
COMP1 |
OVRTM1 |
OVRTM2 |
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Number |
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7:4 |
Reserved; for compatibility with future devices, write zeros to these bits. |
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3:0 |
Setting a bit enables the corresponding interrupt as a multiplexed EPAx interrupt source. |
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The multiplexed EPAx interrupt is enabled by setting its interrupt enable bit in the |
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interrupt mask register (INT_MASK.0 = 1). |
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Figure 10-13. EPA Interrupt Mask 1 (EPA_MASK1) Register
10-27
8XC196Kx, Jx, CA USER’S MANUAL
10.7 DETERMINING EVENT STATUS
In compare mode, an interrupt pending bit is set each time a match occurs on an enabled event (even if the interrupt is specifically masked in the mask register). In capture mode, an interrupt pending bit is set each time a programmed event is captured and the event time moves from the capture buffer to the EPAx_TIME register. If the capture buffer is full when an event occurs, an overrun interrupt pending bit is set.
The EPA0–EPA3 pending bits are located in INT_PEND (Figure 5-5 on page 5-13). The pending bits for the multiplexed interrupts (those that share EPAx) are located in EPA_PEND (Figure 10-14) and EPA_PEND1 (Figure 10-15). If an interrupt is masked, software can still poll the interrupt pending registers to determine whether an event has occurred.
EPA_PEND |
Address: |
1FA2H |
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Reset State: |
0000H |
When hardware detects a pending EPAx interrupt, it sets the corresponding bit in EPA interrupt pending (EPA_PEND or EPA_PEND1) registers. The EPAIPV register contains a number that identifies the highest priority, active, multiplexed interrupt source. When EPAIPV is read, the EPA interrupt pending bit associated with the EPAIPV priority value is cleared.
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15 |
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8 |
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CA, Jx |
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EPA8 |
EPA9 |
OVR0 |
OVR1 |
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7 |
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0 |
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OVR2 |
OVR3 |
— |
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OVR8 |
OVR9 |
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15 |
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8 |
Kx |
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EPA4 |
EPA5 |
EPA6 |
EPA7 |
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EPA8 |
EPA9 |
OVR0 |
OVR1 |
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0 |
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OVR2 |
OVR3 |
OVR4 |
OVR5 |
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OVR6 |
OVR7 |
OVR8 |
OVR9 |
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15:0† |
Any set bit indicates that the corresponding EPAx interrupt source is pending. The bit is |
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cleared when the EPA interrupt priority vector register (EPAIPV) is read. |
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† Bits 2–5 and 12–15 are reserved on the 8XC196CA, Jx devices. For compatibility with future devices, write zeros to these bits.
Figure 10-14. EPA Interrupt Pending (EPA_PEND) Register
10-28