STANDARD AND PTS INTERRUPTS

5.4.2Calculating Latency

The maximum latency occurs when the interrupt request occurs too late for acknowledgment following the current instruction. The following worst-case calculation assumes that the current instruction is not a protected instruction. To calculate latency, add the following terms:

•Time for the current instruction to finish execution (4 state times).

—if this is a protected instruction, the instruction that follows it must also execute before the interrupt can be acknowledged. Add the execution time of the instruction that follows a protected instruction.

•Time for the next instruction to execute. (The longest instruction, NORML, takes 39 state times. However, the BMOV instruction could actually take longer if it is transferring a large block of data. If your code contains routines that transfer large blocks of data, you may want to use the BMOV instruction in your calculation instead of NORML. See Appendix A for instruction execution times.)

•For standard interrupts only, the response time to get the vector and force the call

—11 state times for an internal stack or 13 for an external stack

5.4.2.1Standard Interrupt Latency

The worst-case delay for a standard interrupt is 56 state times (4 + 39 + 11 + 2) if the stack is in external memory. This delay time does not include the time needed to execute the first instruction in the interrupt service routine or to execute the instruction following a protected instruction. Figure 5-2 illustrates the worst-case scenario.

A0136-02

Figure 5-2. Standard Interrupt Response Time

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8XC196Kx, Jx, CA USER’S MANUAL

5.4.2.2PTS Interrupt Latency

The maximum delay for a PTS interrupt is 43 state times (4 + 39). This delay time does not include the added delay if a protected instruction is being executed or if a PTS request is already in progress. See Table 5-4 for execution times for PTS routines.

A0142-01

Figure 5-3. PTS Interrupt Response Time

Table 5-4. Execution Times for PTS Cycles

† Register indicates an access to the register file or peripheral SFR. Memory indicates an access to a memory-mapped register, I/O, or memory. See Table 4-1 on page 4-2 for address information.

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