ARCHITECTURAL OVERVIEW

Chapter 16, “Programming the Nonvolatile Memory,” provides recommended ci rcuits, the corresponding memory maps, and flow diagrams. It also provides procedures for auto programming and describes the commands used for serial port programming.

2.7DESIGN CONSIDERATIONS FOR 87C196CA DEVICES

Some functions that were implemented on 8XC196Kx devices are omitted from the 87C196CA. Table 2-3 lists the pins and signals that are omitted.

Table 2-3. Unsupported Functions in 87C196CA Devices

Follow these recommendations to help maintain hardware and software compatibility between the 87C196CA and future devices.

•Bus width. Since the 87C196CA has no BUSWIDTH pin, the device cannot dynamically switch between 8- and 16-bit bus widths. Configure the CCBs to select either 8- or 16-bit bus width.

•EPA4–EPA7. The 87C196CA has neither the EPA7:4 pins nor the associated functions.

•Slave port. The 87C196CA has no P5.1/SLPCS# pin and no SLPINT signal, so you cannot use the slave port.

•I/O ports. The following port pins do not exist in the 87C196CA: P0.1:0; P1.7:4; P2.3 and P2.5; P5.1 and P5.7; P6.2 and P6.3. Software can still read the associated Px_DIR, Px_MODE, and Px_REG registers. The registers for the removed pins are permanently configured as follows:

—P x_DIR bits are set.

—P x_MODE bits are clear, except P5_MODE.7 is set.

—P x_REG bits are set.

Do not use the bits associated with the removed port pins for conditional branch instructions. Treat these bits as reserved.

•Auto programming. During auto programming, the 87C196CA supports only a 16-bit, zero-wait-state bus configuration.

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8XC196Kx, Jx, CA USER’S MANUAL

2.8DESIGN CONSIDERATIONS FOR 8XC196JQ, JR, JT, AND JV DEVICES

The 8XC196Jx devices are 52-lead versions of 8XC196Kx devices. Some functions were removed to reduce the pin count (Table 2-4).

Table 2-4. Unsupported Functions in 8XC196Jx Devices

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ARCHITECTURAL OVERVIEW

Follow these recommendations to help maintain hardware and software compatibility between 52-lead, 68-lead, and future devices.

•Bus width. Since the 8XC196Jx has neither a WRH# nor a BUSWIDTH pin, the device cannot dynamically switch between 8- and 16-bit bus widths. Program the CCBs to select 8- bit bus mode.

•Wait states. Since the 8XC196Jx has no READY pin, the device cannot rely on a READY signal to control wait states. Program the CCBs to limit the number of wait states (0, 1, 2, or 3).

•EPA4–EPA7. These functions exist in the 8XC196Jx, but the associated pins are omitted. You can use these functions as software timers, to start A/D conversions, or to reset the timers.

•Slave port. Since the 8XC196Jx has no P5.1/SLPCS and P5.4/SLPINT pins, you cannot use the slave port.

•ONCE mode. On the 8XC196JQ and JR, the ONCE mode entry function is multiplexed with P2.6 (P2.6/HLDA#/ONCE) rather than with P5.4 as it is on the 8XC196KQ and KR (P5.4/SLPINT/ONCE).

•NMI. Since the 8XC196Jx has no NMI pin, the nonmaskable interrupt is not supported. Initialize the NMI vector (at location 203EH) to point to a RET instruction. This method provides glitch protection only.

•I/O ports. The following port pins do not exist in the 8XC196Jx: P0.0–P0.1, P1.4–P1.7, P2.3 and P2.5, P5.1 and P5.4–P5.7, P6.2 and P6.3. Software can still read and write the associated Px_REG, Px_MODE, and Px_DIR registers. Configure the registers for the removed pins as follows:

—Clear the corresponding P x_DIR bits. (Configures pins as complementary outputs.)

—Clear the corresponding P x_MODE bits. (Selects I/O port function.)

Do not use the bits associated with the removed port pins for conditional branch instructions. Treat these bits as reserved.

•Auto programming. During auto programming, the 8XC196Jx supports only a 16-bit, zero-wait-state bus configuration.

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3

Programming

Considerations