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Санкт-Петербургский государственный электротехнический университет "ЛЭТИ"

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Электротехника

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8XC196Kx,8XC196Jx,87C196CA microcontroller family user's manual.1995.pdf

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CHAPTER 15 INTERFACING WITH EXTERNAL MEMORY

The device can interface with a variety of external memory devices. It supports either a fixed 8- bit bus width, a fixed 16-bit bus width, or a dynamic 8-bit/16-bit bus width; internal control of wait states for slow external memory devices; a bus-hold protocol that enables external devices to take over the bus; and several bus-control modes. These features provide a great deal of flexibility when interfacing with external memory devices.

In addition to describing the signals and registers related to external memory, this chapter discusses the process of fetching the chip configuration bytes and configuring the external bus. It also provides examples of external memory configurations.

15.1 EXTERNAL MEMORY INTERFACE SIGNALS

Table 15-1 describes the external memory interface signals. For some signals, the pin has an alternate function (shown in the Multiplexed With column). In some cases the alternate function is a port signal (e.g., P2.7). Chapter 6, “I/O Ports,” describes how to configure a pin for its I/O port function and for its special function. In other cases, the signal description includes instructions for selecting the alternate function.

Table 15-1. External Memory Interface Signals

Function	Type	Description	Multiplexed
Name	Type	Description	With
Name			With

AD15:0	I/O	Address/Data Lines	P4.7:0
		These pins provide a multiplexed address and data bus. During the	P3.7:0
		address phase of the bus cycle, address bits 0–15 are presented on
		the bus and can be latched using ALE or ADV#. During the data
		phase, 8- or 16-bit data is transferred. When a bus access is not
		occurring, these pins revert to their I/O port function.

ADV#	O	Address Valid	ALE/P5.0
		This active-low output signal is asserted only during external
		memory accesses. ADV# indicates that valid address information is
		available on the system address/data bus. The signal remains low
		while a valid bus cycle is in progress and is returned high as soon as
		the bus cycle completes.
		An external latch can use this signal to demultiplex the address from
		the address/data bus. A decoder can also use this signal to generate
		chip selects for external memory.

15-1

8XC196Kx, Jx, CA USER’S MANUAL

Table 15-1. External Memory Interface Signals (Continued)

Function	Type				Description		Multiplexed
Name	Type				Description		With
Name							With

ALE	O	Address Latch Enable					ADV#/P5.0
		This active-high output signal is asserted only during external
		memory cycles. ALE signals the start of an external bus cycle and
		indicates that valid address information is available on the system
		address/data bus. ALE differs from ADV# in that it does not remain
		active during the entire bus cycle.
		An external latch can use this signal to demultiplex the address from
		the address/data bus.

BHE#†	O	Byte High Enable					P5.5/WRH#
		The chip configuration register 0 (CCR0) determines whether this pin
		functions as BHE# or WRH#. CCR0.2=1 selects BHE#; CCR0.2=0
		selects WRH#.
		During 16-bit bus cycles, this active-low output signal is asserted for
		word reads and writes and high-byte reads and writes to external
		memory. BHE# indicates that valid data is being transferred over the
		upper half of the system data bus. BHE#, in conjunction with AD0,
		indicates the memory byte that is being transferred over the system
		bus:
		BHE#		AD0	Byte(s) Accessed
		0		0	both bytes
		0		1	high byte only
		1		0	low byte only
		†	This pin is not implemented on the 8XC196Jx device.

BREQ#†	O	Bus Request					P2.3
		This active-low output signal is asserted during a hold cycle when
		the bus controller has a pending external memory cycle.
		The device can assert BREQ# at the same time as or after it asserts
		HLDA#. Once it is asserted, BREQ# remains asserted until HOLD#
		is removed.
		You must enable the bus-hold protocol before using this signal (see
		“Enabling the Bus-hold Protocol (8XC196Kx Only)” on page 15-18).
		†	This pin is not implemented on the 87C196CA, 8XC196Jx devices.

BUSWIDTH†	I	Bus Width					P5.7
		The chip configuration register bits, CCR0.1 and CCR1.2, along with
		the BUSWIDTH pin, control the data bus width. When both CCR bits
		are set, the BUSWIDTH signal selects the external data bus width.
		When only one CCR bit is set, the bus width is fixed at either 16 or 8
		bits, and the BUSWIDTH signal has no effect.
		CCR0.1		CCR1.2 BUSWIDTH
		0		1	N/A	fixed 8-bit data bus
		1		0	N/A	fixed 16-bit data bus
		1		1	high	16-bit data bus
		1		1	low	8-bit data bus
		†	This pin is not implemented on the 87C196CA, 8XC196Jx devices.

15-2

			INTERFACING WITH EXTERNAL MEMORY
		Table 15-1. External Memory Interface Signals (Continued)

	Function	Type	Description	Multiplexed
	Name	Type	Description	With
	Name			With

CLKOUT		O	Clock Output	P2.7
			Output of the internal clock generator. The CLKOUT frequency is ½
			the oscillator frequency input (XTAL1). CLKOUT has a 50% duty
			cycle.

EA#		I	External Access	—
			EA# is sampled and latched only on the rising edge of RESET#.
			Changing the level of EA# after reset has no effect. Accesses to
			special-purpose and program memory partitions are directed to
			internal memory if EA# is held high and to external memory if EA# is
			held low. (See Table 4-1 on page 4-2 for address ranges of special-
			purpose and program memory partitions.)
			EA# also controls program mode entry. If EA# is at VPP voltage
			(typically +12.5 V) on the rising edge of RESET#, the device enters
			programming mode.
			NOTE: When EA# is active, ports 3 and 4 will function only as the
			address/data bus. They cannot be used for standard I/O.
			On devices with no internal nonvolatile memory, always connect EA#
			to VSS.
HLDA#†		O	Bus Hold Acknowledge	P2.6
			This active-low output indicates that the CPU has released the bus
			as the result of an external device asserting HOLD#.
			† The P2.6 pin does not function as HLDA# on the 87C196CA,
			8XC196Jx devices.

HOLD#†		I	Bus Hold Request	P2.5
			An external device uses this active-low input signal to request control
			of the bus. This pin functions as HOLD# only if the pin is configured
			for its special function (see “Bidirectional Port Pin Configurations” on
			page 6-10) and the bus-hold protocol is enabled. Setting bit 7 of the
			window selection register enables the bus-hold protocol.
			† This pin is not implemented on the 87C196CA, 8XC196Jx devices.
INTOUT#†		O	Interrupt Output	AINC#/P2.4
			This active-low output indicates that a pending interrupt requires use
			of the external bus.
			† This pin is not implemented on the 87C196CA, 8XC196Jx devices.
INST†		O	Instruction Fetch	P5.1
			This active-high output signal is valid only during external memory
			bus cycles. When high, INST indicates that an instruction is being
			fetched from external memory. The signal remains high during the
			entire bus cycle of an external instruction fetch. INST is low for data
			accesses, including interrupt vector fetches and chip configuration
			byte reads. INST is low during internal memory fetches.
			† This pin is not implemented on the 87C196CA, 8XC196Jx devices.
RD#		O	Read	P5.3
			Read-signal output to external memory. RD# is asserted only during
			external memory reads.

				15-3
				15-3

8XC196Kx, Jx, CA USER’S MANUAL

Table 15-1. External Memory Interface Signals (Continued)

Function	Type	Description	Multiplexed
Name	Type	Description	With
Name			With

READY†	I	Ready Input	P5.6
		This active-high input signal is used to lengthen external memory
		cycles for slow memory by generating wait states in addition to the
		wait states that are generated internally.
		When READY is high, CPU operation continues in a normal manner
		with wait states inserted as programmed in the chip configuration
		registers. READY is ignored for all internal memory accesses.
		† This pin is not implemented on the 8XC196Jx device.
WR#	O	Write	P5.2/WRL#
		The chip configuration register 0 (CCR0) determines whether this pin
		functions as WR# or WRL#. CCR0.2=1 selects WR#; CCR0.2=0
		selects WRL#.
		This active-low output indicates that an external write is occurring.
		This signal is asserted only during external memory writes.

WRH#†	O	Write High	P5.5/BHE#
		The chip configuration register 0 (CCR0) determines whether this pin
		functions as BHE# or WRH#. CCR0.2=1 selects BHE; CCR0.2=0
		selects WRH#.
		During 16-bit bus cycles, this active-low output signal is asserted for
		high-byte writes and word writes to external memory. During 8-bit
		bus cycles, WRH# is asserted for all write operations.
		† This pin is not implemented on the 87C196CA, 8XC196Jx devices.
WRL#	O	Write Low	P5.2/WR#
		The chip configuration register 0 (CCR0) determines whether this pin
		functions as WR# or WRL#. CCR0.2=1 selects WR#; CCR0.2=0
		selects WRL#.
		During 16-bit bus cycles, this active-low output signal is asserted for
		low-byte writes and word writes. During 8-bit bus cycles, WRL# is
		asserted for all write operations.

15.2 CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES

Two chip configuration registers (CCRs) have bits that set parameters for chip operation and external bus cycles. The CCRs cannot be accessed by code. They are loaded from the chip configuration bytes (CCBs), which have addresses 2018H (CCB0) and 201AH (CCB1).

When the device returns from reset, the bus controller fetches the CCBs and loads them into the CCRs. From this point, these CCR bit values define the chip configuration until the device is reset again. The CCR bits are described in Figures 15-1 and 15-2.

15-4

INTERFACING WITH EXTERNAL MEMORY

CCR0	Address:	2018H
	Reset State:	XXH

The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus width.

LOC1

LOC0

IRC1

IRC0

ALE

BW0

Bit

Function

Number

Mnemonic

7:6

LOC1:0

Lock Bits

Determine the programming protection scheme for internal memory.

LOC1 LOC0

read and write protect

read protect only

write protect only

no protection

5:4

IRC1:0

Internal Ready Control

These two bits, along with IRC2 (CCR1.1), limit the number of wait states

that can be inserted while the READY pin is held low. Wait states are

inserted into the bus cycle either until the READY pin is pulled high or

until this internal number is reached.

IRC2

IRC1

IRC0

zero wait states

illegal

one wait state

two wait states

three wait states

infinite†

† This mode is unavailable on the 8XC196Jx device. On this device, the

READY pin is not implemented. Therefore, the number of wait states

inserted into the bus cycle is determined only by the IRC2:0 bit settings.

Figure 15-1. Chip Configuration 0 (CCR0) Register

15-5

8XC196Kx, Jx, CA USER’S MANUAL

CCR0 (Continued)	Address:	2018H
	Reset State:	XXH

LOC1

LOC0

IRC1

IRC0

ALE

BW0

Bit

Function

Number

Mnemonic

ALE

Address Valid Strobe and Write Strobe

These bits define which bus-control signals will be generated during

external read and write cycles.

ALE WR

address valid with write strobe mode

(ADV#, RD#, WRL#, WRH#)†

address valid strobe mode

(ADV#, RD#, WR#, BHE#)†

write strobe mode

(ALE, RD#, WRL#, WRH#)†

standard bus-control mode

(ALE, RD#, WR#, BHE#)†

†

On the 8XC196Jx device, the BHE#/WRH# pin is not implemented.

BW0

Buswidth Control

This bit, along with the BW1 bit (CCR1.2), selects the bus width.

BW1 BW0

illegal

16-bit only

8-bit only

BUSWIDTH pin controlled†

†

This mode is unavailable on the 87C196CA, 8XC196Jx devices. The

BUSWIDTH pin is not implemented.

Powerdown Enable

Controls whether the IDLPD #2 instruction causes the device to enter

powerdown mode. Clearing this bit at reset can prevent accidental entry

into powerdown mode.

= enable powerdown mode

= disable powerdown mode

Figure 15-1. Chip Configuration 0 (CCR0) Register (Continued)

15-6

INTERFACING WITH EXTERNAL MEMORY

CCR1	Address:	201AH
	Reset State:	XXH

The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width.

	7										0
CA, Jx, KQ, KR			1		1	0	1	WDE	BW1	IRC2	0
		7									0
KS, KT
KS, KT		MSEL1		MSEL0		0	1	WDE	BW1	IRC2	0

Bit		Bit						Function
Number	Mnemonic							Function
Number	Mnemonic

7:6	1			To guarantee device operation, write ones to these bits.
	(CA, Jx, KQ,
	KR)

	MSEL1:0			External Access Timing Mode Select
	(KS, KT)			These bits control the bus-timing modes.
				These bits control the bus-timing modes.
				MSEL1 MSEL0
				0	0		standard mode plus one wait state
				0	1		long read/write
				1	0		long read/write with early address
				1	1		standard mode

5	0			To guarantee device operation, write zero to this bit.

4	1			To guarantee device operation, write one to this bit.

3	WDE			Watchdog Timer Enable
				Selects whether the watchdog timer is always enabled or enabled the first
				time it is cleared.
				1	= enabled first time it is cleared
				0	= always enabled

2	BW1			Buswidth Control
				This bit, along with the BW0 bit (CCR0.1), selects the bus width.
				BW1 BW0
				0	0	illegal
				0	1	16-bit only
				1	0	8-bit only
				1	1	BUSWIDTH pin controlled†
				†	This mode is unavailable on the 87C196CA, 8XC196Jx devices. The
				BUSWIDTH pin is not implemented.

Figure 15-2. Chip Configuration 1 (CCR1) Register

15-7

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