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15.5 BUS-HOLD PROTOCOL (8XC196KQ, KR, KS, KT ONLY)

The 8XC196Kx device supports a bus-hold protocol that allows external devices to gain control of the address/data bus. The protocol uses three signals, all of which are port 2 special functions: HOLD#/P2.5 (hold request), HLDA#/P2.6 (hold acknowledge), and BREQ#/P2.3 (bus request). When an external device wants to use the device bus, it asserts the HOLD# signal. HOLD# is sampled while CLKOUT is low. The device responds by releasing the bus and asserting HLDA#. During this hold time, the address/data bus floats, and signals ALE, RD#, WR#/WRL#, BHE#/WRH#, and INST are weakly held in their inactive states. Figure 15-8 shows the timing for bus-hold protocol, and Table 15-3 on page 15-18 lists the timing parameters and their definitions. Refer to the data sheet for timing parameter values.

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8XC196Kx, Jx, CA USER’S MANUAL

Table 15-3. HOLD#, HLDA# Timing Definitions

When the external device is finished with the bus, it relinquishes control by driving HOLD# high. In response, the 8XC196Kx drives HLDA# high and assumes control of the bus.

If the 8XC196Kx has a pending external bus cycle while it is in hold, it asserts BREQ# to request control of the bus. After the external device responds by driving HOLD# high, the 8XC196Kx exits hold and then deasserts BREQ# and HLDA#.

NOTE

If the 8XC196Kx receives an interrupt request while it is in hold, the 8XC196Kx asserts INTOUT# only if it is executing from internal memory. If the 8XC196Kx needs to access external memory, it asserts BREQ# and waits until the external device deasserts HOLD# to assert INTOUT#. If the 8XC196Kx receives an interrupt request as it is going into hold (between the time that an external device asserts HOLD# and the time that the 8XC196Kx responds with HLDA#), the 8XC196Kx asserts INTOUT# and keeps it asserted until the external device deasserts HOLD#.

15.5.1 Enabling the Bus-hold Protocol (8XC196Kx Only)

To use the bus-hold protocol, you must configure P2.3/BREQ#, P2.5/HOLD#, and P2.6/HLDA# to operate as special-function signals. BREQ# and HLDA# are active-low outputs; HOLD# is an active-low input.

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You must also set the hold enable bit (HLDEN) in the window selection register (WSR.7) to enable the bus-hold protocol. Once the bus-hold protocol has been selected, the port functions of P2.3, P2.5, and P2.6 cannot be selected without resetting the device. (During the time that the pins are configured to operate as special-function signals, their special-function values can be read from the P2_PIN.x bits.) However, the hold function can be dynamically enabled and disabled as described in “Disabling the Bus-hold Protocol (8XC196Kx Only).”

15.5.2 Disabling the Bus-hold Protocol (8XC196Kx Only)

To disable hold requests, clear WSR.7. The device does not take over the bus immediately after HLDEN is cleared. Instead, it waits for the current HOLD# request to finish and then disables the bus-hold feature and ignores any new requests until the bit is set again.

Sometimes it is important to prevent another device from taking control of the bus while a block of code is executing. One way to protect a code segment is to clear WSR.7 and then execute a JBC instruction to check the status of the HLDA# signal. The JBC instruction prevents the RALU from executing the protected block until current HOLD# requests are serviced and the hold feature is disabled. This is illustrated in the following code:

15.5.3 Hold Latency (8XC196Kx Only)

When an external device asserts HOLD#, the device finishes the current bus cycle and then asserts HLDA#. The time it takes the device to assert HLDA# after the external device asserts HOLD# is called hold latency (see Figure 15-8). Table 15-4 lists the maximum hold latency for each type of bus cycle.

Table 15-4. Maximum Hold Latency

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