8XC196Kx, Jx, CA USER’S MANUAL

The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width.

Figure 15-2. Chip Configuration 1 (CCR1) Register (Continued)

15.3 BUS WIDTH AND MULTIPLEXING

The external bus can operate as either a 16-bit multiplexed address/data bus or as a multiplexed 16-bit address/8-bit data bus (Figure 15-3).

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A3068-01

Figure 15-3. Multiplexing and Bus Width Options

After reset, but before the CCB fetch, the device is configured for 8-bit bus mode, regardless of the BUSWIDTH input. The upper address lines (AD15:8) are weakly driven throughout the CCB0 and CCB1 bus cycles. To prevent bus contention, neither pull-ups nor pull-downs should be used on AD15:8. Also, the upper bytes of the CCB words (locations 2019H and 201BH) should be loaded with 20H. If the external memory outputs 20H on its high byte, there will be no bus contention.

After the CCBs are loaded into the CCRs, the values of BW0 and BW1 define the data bus width as either a fixed 8-bit, a fixed 16-bit, or a dynamic 16-bit/8-bit bus width controlled by the BUSWIDTH signal (The BW0 and BW1 bits are defined in Figures 15-1 and 15-2).

If BW0 is clear and BW1 is set, the bus controller is locked into an 8-bit bus mode. In comparing an 8-bit bus system to a 16-bit bus system, expect some performance degradation. In a 16-bit bus system, a word fetch is done with a single word fetch. However, in an 8-bit bus system, a word fetch takes an additional bus cycle because it must be done with two byte fetches.

If BW0 is set and BW1 is clear, the bus controller is locked into a 16-bit bus mode. If both BW0 and BW1 are set, the BUSWIDTH signal controls the bus width. The bus is 16 bits wide when BUSWIDTH is high and 8 bits wide when BUSWIDTH is low. The BUSWIDTH signal is sampled after the address is on the bus, as shown in Figure 15-4.

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Figure 15-4. BUSWIDTH Timing Diagram

The BUSWIDTH signal can be used in numerous applications. For example, a system could store code in a 16-bit memory device and data in an 8-bit memory device. The BUSWIDTH signal could be tied to the chip-select input of the 8-bit memory device (shown in Figure 15-12 on page 15-23). When BUSWIDTH is low, it enables 8-bit bus mode and selects the 8-bit memory device. When BUSWIDTH is high, it enables 16-bit bus mode and deselects the 8-bit memory device.

15.3.1 Timing Requirements for BUSWIDTH

When using BUSWIDTH to dynamically change between 8-bit and 16-bit bus widths, setup and hold timings must be met for proper operation (see Figure 15-4). Because a decoded, valid address is used to generate the BUSWIDTH signal, the setup time is specified relative to the address being valid. This specification, TAVGV, indicates how much time one has to decode the valid address and generate a valid BUSWIDTH signal.

BUSWIDTH must be held valid until the minimum hold specification, TCLGX, has been met. Typically this hold time is 0 ns minimum after CLKOUT goes low. In all cases, refer to the data sheet

for current specifications for TAVGV and TCLGX.

NOTE

Earlier HMOS devices used a BUSWIDTH setup timing that was referenced to

the falling edge of ALE (TLLGV). This specification is not meaningful for CMOS devices, which use an internal two-phase clock; it is included for

comparison only.

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15.3.2 16-bit Bus Timings

When the device is configured to operate in the 16-bit bus-width mode, lines AD15:0 form a 16bit multiplexed address/data bus. Figure 15-5 shows an idealized timing diagram for the external read and write cycles. (Comprehensive timing specifications are shown in Figure 15-24).

The rising edge of the address latch enable (ALE) indicates that the device is driving an address onto the bus (AD15:0). The device presents a valid address before ALE falls. The ALE signal is used to strobe a transparent latch (such as a 74AC373), which captures the address from AD15:0 and holds it while the bus controller puts data onto AD15:0.

For 16-bit read cycles, the bus controller floats the bus and then drives RD# low so that it can receive data. The external memory must put data (Data In) onto the bus before the rising edge of RD#. The data sheet specifies the maximum time the memory device has to output valid data after RD# is asserted. When INST is asserted, it indicates that the read operation is an instruction fetch.

For 16-bit write cycles, the bus controller drives WR# low, then puts data onto the bus. The rising edge of WR# signifies that data is valid. At this time, the external system must latch the data.

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8XC196Kx, Jx, CA USER’S MANUAL

XTAL1

CLKOUT

ALE

Valid

BUSWIDTH

Bus

AD15:0 Address Out Data In

(Read)

RD#

Bus

AD15:0 Address Out Data Out

(Write)

WR#

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Figure 15-5. Timings for 16-bit Buses

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