8XC196Kx, Jx, CA USER’S MANUAL

9.4SLAVE PORT MODES

The slave port can operate in either standard slave mode or shared memory mode (8XC196KS and KT only). In both modes, the master and slave share a 256-byte block of memory located anywhere within the slave’s memory space. Data written is stored in the slave’s P3_PIN register; data to be read is stored in the slave’s P3_REG register. The standard slave mode supports either a demultiplexed or a multiplexed bus and uses the command buffer full (CBF) interrupt. The shared memory mode supports only a multiplexed bus and uses the input buffer empty (IBE) and output buffer full (OBF) interrupts. In both modes, the interrupts must be processed by a software interrupt service routine.

9.4.1Standard Slave Mode Example

In standard slave mode, the master and slave share a 256-byte block of memory. The high byte of the address (the base address) selects the location within the slave’s memory space. The master writes the low byte of the address to the slave’s command register (SLP_CMD). This mode can be used with either a multiplexed or a demultiplexed bus.

In this example, the master and slave share a 256-byte block of memory from 0400–04F FH. The master device has arbitrary external memory locations that are dedicated to slave port accesses.

9.4.1.1Master Device Program

The following code segment illustrates the simple method for writing to the slave.

The master first writes data to the P3_PIN register, which clears the IBE flag in the slave’s SLP_STAT register and pulls SLPINT low. This notifies the slave to perform a data write at the address BASE + SLP_CMD.

The following code segment illustrates the equally simple method for reading from the slave.

9-8

SLAVE PORT

The master first reads the P3_REG register. This ensures that the slave’s P3_REG is indeed empty, clears the OBF flag, and pulls SLPINT low. Next, it loads the address it wants to read into the SLP_CMD register. This causes a CBF interrupt in the slave processor. The slave reads that location and stores the data in P3_REG, which sets the OBF flag and forces SLPINT high. This notifies the master to read the P3_REG register.

9.4.1.2Slave Device Program

Once the slave port and ports 3 and 5 are initialized, the slave device program is strictly interrupt driven. When the slave device receives a byte in the SLP_CMD register, the command buffer full (CBF) interrupt is generated. The CBF interrupt service routine reads the OBF and IBE flags in the SLP_STAT register to determine whether the master device is sending data or requesting a data read. For a data-read request, the master device clears P3_REG, which clears the OBF flag, before it loads SLP_CMD. For a data write, the master writes P3_PIN, which clears the IBE flag, before it loads SLP_CMD. Therefore, only one of the two flags is clear when the CBF interrupt service routine is entered.

If the IBE flag is clear (the input buffer, P3_PIN, is full), the slave moves the data from the P3_PIN register to the specified address. If the OBF flag is clear (the output buffer, P3_REG, is empty), the slave moves the data from the specified address to the P3_REG register so that the master can read it.

The following code segment shows the CBF interrupt service routine. The CBF interrupt must be enabled and interrupts must be globally enabled for this routine to function.

9-9

8XC196Kx, Jx, CA USER’S MANUAL

9.4.1.3Demultiplexed Bus Timings

The master processor performs two bus cycles for each byte written and three bus cycles for each byte read. For the slave device, only five bytes are used (two bytes for the pointer to the open memory window, two bytes for the temporary storage register, and one byte for the base address). A read requires 91 state times (11.375 µs at 16 MHz) and a write requires 86 state times ( 10.750 µs at 16 MHz). These times do not include interrupt latency (see “Interrupt Latency” on page 5-7). Figure 9-4 shows relative timing relationships. Consult the datasheet for actual timing specifications.

1.Connect to master's A1 signal.

2.Rising edge associated with either

–Read ready (write to P3_REG)

–Write complete (read of P3_PIN)

A0307-02

Figure 9-4. Standard Slave Mode Timings (Demultiplexed Bus)

9-10