15.5 BUS WIDTH AND MULTIPLEXING

INTERFACING WITH EXTERNAL MEMORY

A system can incorporate external devices that operate with different bus widths and multiplexing. The chip-select output assigned to the address being accessed determines the bus parameters for that particular bus cycle. Figure 15-9 shows the address and data bus configurations for the four combinations of bus width and multiplexing. For detailed waveforms, see “16-bit Bus Timings” on page 15-25 and “System Bus AC Timing Specifications” on page 15-40.

† AD15:8 drive the data currently on the high byte of the internal bus.

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Figure 15-9. Bus Activity for Four Types of Buses

In demultiplexed mode (top of Figure 15-8 and Figure 15-9), the external device receives the address from A20:0. In a 16-bit system, the data is on AD15:0. In an 8-bit system, the data is on AD7:0, and AD15:8 drive the data currently on the high byte of the internal bus.

In multiplexed mode (bottom half of Figure 15-8 and Figure 15-9), both A20:0 and AD15:0 drive the address. A20:0 drive the address throughout the entire bus cycle. For a 16-bit bus width, AD15:0 drive the address for the first half of the bus cycle and drive or receive data during the second half. In the 8-bit case, AD15:8 drive the address during the entire bus cycle.

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In multiplexed mode, with the full address on the bus for only half of the cycle, the external device has less time to receive it and to respond. As a result, for the same bus-cycle length (4t) a multiplexed system requires a faster external device (unless wait states are added to the bus cycle). Although the multiplexed mode has this disadvantage, it is useful for compatibility with devices designed for multiplexed operation.

In a 16-bit system (left side of Figure 15-8 and Figure 15-9) one data word can be transferred over AD15:0 in a single bus cycle. In an 8-bit system, one data word is transferred as two bytes over AD7:0 in successive bus cycles, and AD15:8 drive the upper eight address bits for the entire bus cycle.

The flexibility of the chip-select unit enables you to specify the bus width, the number of wait states, and a multiplexed or demultiplexed bus for each of the three chip-select outputs. The system in Figure 15-5 on page 15-15 illustrates a mixture of 16-bit and 8-bit devices with different numbers of wait states.

15.5.1 A 16-bit Example System

Figure 15-10 shows a 16-bit system in demultiplexed mode. The 256K×16 flash memory receives the address on A18:1; data is transferred on AD15:0. Using the WR# signal as shown, this system writes words, not single bytes, to the memory. (Using WRL# and WRH#, you can write single bytes on a 16-bit bus.)

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INTERFACING WITH EXTERNAL MEMORY

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Figure 15-10. 16-bit External Devices in Demultiplexed Mode

15.5.2 16-bit Bus Timings

Figure 15-11 shows idealized 16-bit external-bus timings for the microcontroller. The signals are divided into two groups: signals for a demultiplexed bus (top) and signals for a multiplexed bus (bottom). Several bus signals are omitted from the figure to focus on a comparison of multiplexed and demultiplexed buses. The timing parameters are addressed in “Comparison of Multiplexed and Demultiplexed Buses” on page 15-29. Comprehensive timing specifications for the microcontroller are shown in Figures 15-19 and 15-20.

CLKOUT and ALE are the same in multiplexed and demultiplexed buses. The CLKOUT period is as programmed in the CLKOUT_CON register (see “External Timing” on page 2-12). The figures assume the CLKOUT period is twice the internal oscillator period (2t). The bus cycles shown here, which have no wait states, require two CLKOUT periods (two state times, or 4t).

The rising edge of the address latch enable (ALE) signal indicates that the microcontroller is driving an address onto the bus (A20:16 and AD15:0 for a multiplexed bus, A20:0 for a demultiplexed bus). The microcontroller presents a valid address before ALE falls. In a multiplexed system, the ALE signal is used to strobe a transparent latch (such as a 74AC373), which captures the address from AD15:0 and holds it while data is transferred on AD15:0.

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Demultiplexed

WR#

AD15:0

Data In Address Out Data Out Address Out

(write)

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Figure 15-11. Timings for Multiplexed and Demultiplexed 16-bit Buses

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