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8xC196EA microcontroller user's manual.1998.pdf
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STANDARD AND PTS INTERRUPTS

 

 

 

Timer/Counter Unit

 

 

 

 

 

 

 

Timer 3

 

 

Timer 4

 

 

 

 

 

 

 

 

Timer 1

Timer4:1 Overflow

 

 

 

 

 

 

 

Timer 2

 

 

 

 

 

 

 

 

 

 

 

Output/

OS7:0 Event

 

 

 

 

 

 

 

OS7:0

 

 

 

 

Simulcapture

 

 

 

 

 

 

 

 

 

Channels 0-7

 

 

 

 

 

 

 

 

 

 

EPA2:0 Overrun

 

 

 

 

 

 

 

Capture/Compare

 

EPA16 Event

EPA16:0

 

 

 

 

 

Channels 0-16

EPA15:0 Event

 

 

 

 

 

 

 

 

 

 

EPA16:3 Overrun

 

 

 

 

 

 

 

 

 

Interrupt Handler 1

(PIH1)

Peripheral

 

 

 

PIH1

 

 

Standard

 

 

Interrupt

 

 

PIH1 PTS

Handler 0

 

Interrupt

(PIH0)

PIH0

Interrupt

Standard

 

 

Peripheral

 

Interrupt

 

PIH0 PTS

 

 

 

 

Interrupt

EPAx_OVR Interrupt

A3388-01

Figure 6-5. Peripheral Interrupt Handler (PIH) Interrupt Sources

6.3.5End-of-PTS Interrupts

When the PTSCOUNT register decrements to zero at the end of a single transfer, block transfer, or missed-event routine, hardware clears the corresponding bit in the PTSSEL register (Figure 6-12 on page 6-23), which disables PTS service for that interrupt. It also sets the corresponding PTSSRV bit, requesting an end-of-PTS interrupt. An end-of-PTS interrupt has the same priority as a corresponding standard interrupt. The interrupt controller processes it with an interrupt service routine that is stored in the memory location pointed to by the standard interrupt vector. For example, the PTS services the SIO1 transmit (TI1) interrupt if PTSSEL.4 is set. The PTS interrupt vectors through FF2048H, but the corresponding end-of-PTS interrupt vectors through FF2008H, the standard TI1 interrupt vector. When the end-of-PTS interrupt vectors to the interrupt service routine, hardware clears the PTSSRV bit. The end-of-PTS interrupt service routine should reinitialize the PTSCB, if required, and set the appropriate PTSSEL bit to re-enable PTS interrupt service.

6.4INTERRUPT LATENCY

Interrupt latency is the total delay between the time that the interrupt request is generated (not acknowledged) and the time that the microcontroller begins executing either the interrupt service routine or the PTS interrupt service routine. A delay occurs between the time that the interrupt request is detected and the time that it is acknowledged. An interrupt request is acknowledged when the current instruction or uninterruptable instruction sequence completes execution. If the interrupt request occurs during one of the last four state times of the instruction, it may not be acknowledged until after the next instruction finishes. This additional delay occurs because instructions are prefetched from external memory and assembled a minimum of four state times before they are executed. Thus, the maximum delay between interrupt request and acknowledgment

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