ARCHITECTURAL OVERVIEW

2.3FUNCTIONAL OVERVIEW

Figure 2-3 is a simplified block diagram that shows the major blocks within the microcontroller. The remainder of this section describes those blocks.

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Figure 2-3. 83C196EA Simplified Block Diagram

2.3.1Core

The core of the microcontroller (Figure 2-4) consists of the central processing unit (CPU) and memory controller. A 16-bit internal bus connects the CPU to both the memory controller and the interrupt controller. An extension of this bus connects the CPU to the internal peripheral modules. In addition, an 8-bit internal bus transfers instruction bytes from the memory controller to the instruction register in the RALU.

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8XC196EA USER’S MANUAL

Figure 2-4. Block Diagram of the Core

2.3.1.1CPU

The CPU contains the register arithmetic-logic unit (RALU) and the register file. CPU instructions move from the 8-byte prefetch queue in the memory controller into the RALU’s instruction register. The microcode engine decodes the instructions and then generates the sequence of events that cause desired functions to occur.

2.3.1.2Register Arithmetic-logic Unit (RALU)

The RALU contains the microcode engine, the 16-bit arithmetic logic unit (ALU), the master program counter (PC), the processor status word (PSW), and several registers. The microcode engine instructs the RALU to perform operations using bytes, words, or double-words from the register file.

The 24-bit master program counter (PC) provides a linear, nonsegmented 16-Mbyte memory space. (For compatibility with earlier microcontrollers, the PC can be configured as 16 bits wide.) Only 21 of the internal address bits are implemented with external pins, so you can physically address only 2 Mbytes. The master PC contains the address of the next instruction and has a builtin incrementer that automatically loads the next sequential address. However, if a jump, interrupt, call, or return changes the address sequence, the ALU loads the correct address into the master PC.

The processor status word (PSW) contains one bit (PSW.1) that globally enables or disables servicing of all maskable interrupts, one bit (PSW.2) that enables or disables the peripheral transaction server (PTS), and six Boolean flags that reflect the state of your program. See Table A-2 on page A-4 for a description of the status flags.)

The registers in the RALU are the instruction register, a constants register, a bit-select register, a loop counter, and three temporary registers (the upper-word, lower-word, and second-operand registers). The bit-select register is 3 bits, and the loop counter is 6 bits. All other registers in the

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ARCHITECTURAL OVERVIEW

RALU are either 16 or 17 bits (16 bits plus a sign extension). Some of these registers can reduce the ALU’s workload by performing simple operations.

CPU instructions move into the instruction register from the 8-byte prefetch queue in the memory controller. The microcode engine decodes the instructions and instructs the RALU to perform the required operations.

The RALU speeds up calculations by storing constants (e.g., 0, 1, and 2) in the constants register so that they are readily available when complementing, incrementing, or decrementing bytes or words. Based on the bit-select register, the constants register generates single-bit masks for bittest instructions. The six-bit loop counter counts repetitive shifts.

The RALU uses the upperand lower-word registers together for the 32-bit instructions and as temporary registers for many instructions. These registers have their own shift logic and are used for operations that require logical shifts, including normalize, multiply, and divide operations. The second-operand register stores the second operand for two-operand instructions, including the multiplier during multiply operations and the divisor during divide operations. During subtraction operations, the output of this register is complemented before it is moved into the ALU.

The RALU performs most calculations for the microcontroller, but it does not use an accumulator. Instead it operates directly on the lower register file, which essentially provides 256 accumulators. Because data does not flow through a single accumulator, the microcontroller’s code executes faster and more efficiently than, for example, an 80C186 microprocessor.

MCS 96 microcontrollers combine a large set of general-purpose registers with a three-operand instruction format. This format allows a single instruction to specify two source registers and a separate destination register. For example, the following instruction multiplies two 16-bit variables and stores the 32-bit result in a third variable.

An 80C186 microprocessor requires four instructions to accomplish the same operation. The following example shows the equivalent code for an 80C186 microprocessor:

2.3.1.3Register File

The register file is divided into an upper and a lower file. In the lower register file, the lowest 24byte section is allocated to the CPU’s special-function registers (SFRs) and the stack pointer, while the remainder is available as general-purpose register RAM. The upper register file contains only general-purpose register RAM. The register RAM can be accessed as bytes, words, or double-words.

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