8XC196EA USER’S MANUAL

is four state times plus remaining instruction fetch time and the execution time of the next instruction.

When a standard interrupt request is acknowledged, the hardware clears the interrupt pending bit and forces a call to the address contained in the corresponding interrupt vector. When a PTS interrupt request is acknowledged, the hardware immediately vectors to the PTSCB and begins executing the PTS routine.

6.4.1Situations that Increase Interrupt Latency

If an interrupt request occurs while any of the following instructions are executing, the interrupt will not be acknowledged until after the next instruction is executed:

•the signed prefix opcode (FE) for the two-byte, signed multiply and divide instructions

•a protected instruction: DI, EI, DPTS, EPTS, POPA, POPF, PUSHA, PUSHF (see Appendix A for descriptions of these instructions)

•a read-modify-write instruction: AND, ANDB, OR, ORB, XOR, XORB

•the unimplemented opcode interrupt and the software trap interrupt

Each PTS cycle within a PTS routine cannot be interrupted. A PTS cycle is the entire PTS response to a single interrupt request. In block transfer mode, a PTS cycle consists of the transfer of an entire block of bytes or words. This means a worst-case latency of 500 states if you assume a block transfer of 32 words from one external memory location to another. See Table 6-6 on page 6-18 for PTS cycle execution times.

6.4.2Calculating Latency

The maximum latency occurs when the interrupt request occurs too late (four states before the current instruction finishes executing) for acknowledgment following the current instruction. The following worst-case calculation assumes that the current instruction is not a protected instruction To calculate latency, add the following terms:

•Time for the interrupt request to be detected (4 state times).

—One state each to clock edge, synchronize the interrupt, prioritize the interrupt request, and request interrupt service.

•Time for the current instruction to finish execution (4 state times).

—If this is a protected instruction, the instruction that follows it must also execute before the interrupt can be acknowledged. Add the execution time of the instruction that follows a protected instruction.

•Time for the next instruction to execute. (See Appendix A for instruction execution times.)

—The longest instruction, NORML, takes 39 state times. However, the BMOV instruction could actually take longer if it is transferring a large block of data. If your code contains routines that transfer large blocks of data, you may get a more accurate worst-case value if you use the BMOV execution time in your calculation instead of NORML.

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