- •CONTENTS
- •FIGURES
- •TABLES
- •1.1 Manual Contents
- •1.2 Notational Conventions and Terminology
- •1.3 Related Documents
- •1.4 Application Support Services
- •2.1 Typical Applications
- •2.2 Microcontroller Features
- •2.3 Functional Overview
- •2.3.1 Core
- •2.3.1.3 Register File
- •2.3.2 Memory Controller
- •2.4 Internal Timing
- •2.4.1 Clock and Power Management Logic
- •2.4.2 Internal Timing
- •2.4.2.1 Clock Failure Detection Logic
- •2.4.2.2 External Timing
- •2.4.2.3 Power Management Options
- •2.4.3 Internal Memory
- •2.4.4 Serial Debug Unit
- •2.4.5 Interrupt Service
- •2.5 Internal Peripherals
- •2.5.1 I/O Ports
- •2.5.2 Serial I/O (SIO) Port
- •2.5.3 Synchronous Serial I/O (SSIO) Port
- •2.5.4 Event Processor Array (EPA) and Timer/Counters
- •2.5.7 Stack Overflow Module
- •2.5.8 Watchdog Timer
- •2.6 Special Operating Modes
- •2.7 Chip Configuration Registers
- •3.1 Overview of the Instruction Set
- •3.1.1 BIT Operands
- •3.1.2 BYTE Operands
- •3.1.4 WORD Operands
- •3.1.5 INTEGER Operands
- •3.1.9 Converting Operands
- •3.1.10 Conditional Jumps
- •3.1.11 Floating-Point Operations
- •3.1.12 Extended Instructions
- •3.2 Addressing Modes
- •3.2.1 Direct Addressing
- •3.2.2 Immediate Addressing
- •3.2.3 Indirect Addressing
- •3.2.3.1 Extended Indirect Addressing
- •3.2.3.2 Indirect Addressing with Autoincrement
- •3.2.3.3 Extended Indirect Addressing with Autoincrement
- •3.2.3.4 Indirect Addressing with the Stack Pointer
- •3.2.4 Indexed Addressing
- •3.2.4.3 Extended Indexed Addressing
- •3.2.4.4 Zero-indexed Addressing
- •3.3 Considerations for Crossing Page Boundaries
- •3.4 Software Protection Features and Guidelines
- •4.1 Memory Map Overview
- •4.2 Memory Partitions
- •4.2.1 External Memory
- •4.2.2 Internal ROM
- •4.2.2.1 Program Memory in Page FFH
- •4.2.2.3 Reserved Memory Locations
- •4.2.2.4 Interrupt, PIH, and PTS Vectors
- •4.2.2.5 Chip Configuration Bytes
- •4.2.3 Internal RAM (Code RAM)
- •4.2.4.2 Peripheral SFRs
- •4.2.5 Register File
- •4.2.5.2 Stack Pointer (SP)
- •4.3 Windowing
- •4.3.1 Selecting a Window
- •4.3.2 Addressing a Location Through a Window
- •4.3.2.4 Unsupported Locations Windowing Example
- •4.3.2.5 Using the Linker Locator to Set Up a Window
- •4.3.3 Windowing and Addressing Modes
- •4.4 Controlling Read Access to the Internal ROM
- •4.5 Remapping Internal ROM
- •5.1 Functional Overview
- •5.2 Stack Operations
- •5.3 Stack Overflow Module Registers
- •5.4 Programming the Stack Overflow Module
- •5.4.1 Initializing the Stack Pointer
- •5.4.2 Enabling the Stack Overflow Module and Specifying Stack Boundaries
- •6.1 Overview of the Interrupt Control Circuitry
- •6.2 Interrupt Signals and Registers
- •6.3 Interrupt Sources, Priorities, and Vector Addresses
- •6.3.1 PIH Interrupt Sources, Priorities, and Vector Addresses
- •6.3.1.1 Using Software to Provide the Vector Address
- •6.3.1.2 Providing the Vector Address in Response to a CPU Request
- •6.3.2 Special Interrupts
- •6.3.2.1 Unimplemented Opcode
- •6.3.2.2 Software Trap
- •6.3.2.4 Stack Overflow
- •6.3.3 External Interrupt Signal
- •6.3.4 Shared Interrupt Requests
- •6.4 Interrupt Latency
- •6.4.1 Situations that Increase Interrupt Latency
- •6.4.2 Calculating Latency
- •6.4.2.2 PTS Interrupt Latency
- •6.5 Programming the Interrupts
- •6.5.1 Modifying Interrupt Priorities
- •6.5.2 Determining the Source of an Interrupt
- •6.6 Initializing the PTS Control Blocks
- •6.6.1 Specifying the PTS Count
- •6.6.2 Selecting the PTS Mode
- •6.6.3 Single Transfer Mode
- •6.6.4 Block Transfer Mode
- •6.6.5 Dummy Mode
- •7.1 I/O Ports Overview
- •7.2 Configuring the Port Pins
- •7.2.2 Configuring Ports 3 and 4 (Address/Data Bus)
- •7.2.3 Port Configuration Example
- •7.3.1 Address and Data Signals (Ports 3, 4, and EPORT)
- •7.3.1.1 EPORT Status During Reset, CCB Fetch, Idle, Powerdown, and Hold
- •7.3.5 External Interrupt Signal (Port 2)
- •7.3.6 PWM Signals (Port 11)
- •7.3.7 Serial I/O Port Signals (Ports 2 and 7)
- •7.3.8 Special Operating Mode Signal (Port 5 Pin 7)
- •7.3.9 Synchronous Serial I/O Port Signals (Port 10)
- •7.4 I/O Port Internal Structures
- •7.4.3 Internal Structure for Ports 3 and 4 (Address/Data Bus)
- •8.1 Serial I/O (SIO) Port Functional Overview
- •8.2 Serial I/O Port Signals and Registers
- •8.3 Serial Port Modes
- •8.3.1 Synchronous Mode (Mode 0)
- •8.3.2 Asynchronous Modes (Modes 1, 2, and 3)
- •8.3.2.1 Mode 1
- •8.3.2.2 Mode 2
- •8.3.2.3 Mode 3
- •8.3.2.4 Multiprocessor Communications
- •8.4 Programming the Serial Port
- •8.4.1 Configuring the Serial Port Pins
- •8.4.2 Programming the Control Register
- •8.4.3 Programming the Baud Rate and Clock Source
- •8.4.4 Enabling the Serial Port Interrupts
- •8.4.5 Determining Serial Port Status
- •CHAPTER 9 Synchronous Serial I/O (SSIO) Port
- •9.1 SSIO Port Overview
- •9.1.1 Standard Mode
- •9.1.2 Duplex Mode
- •9.2 SSIO pORT sIGNALS AND rEGISTERS
- •9.3 ssio Port Operation
- •9.3.1 Transmitting and Receiving Data
- •9.3.1.1 Normal Transfers (All Modes)
- •9.3.1.2 Handshaking Transfers (Standard Mode Only)
- •9.4 Programming the SSIO Port
- •9.4.1 Configuring the SSIO Port Pins
- •9.4.2 Configuring the SSIO Registers
- •9.4.2.1 The SSIO Baud (SSIO_BAUD) Register
- •9.4.2.3 The SSIO 0 Clock (SSIO0_CLK) Register
- •9.4.2.4 The SSIO 1 Clock (SSIO1_CLK) Register
- •9.4.3 Enabling the SSIO Interrupts
- •9.5 Programming Considerations
- •9.5.2 Standard Mode Considerations
- •9.5.3 Duplex Mode Considerations
- •10.1 PWM FUNCTIONAL OVERVIEW
- •10.2 PWM Signals and Registers
- •10.3 pwm operation
- •10.4 Programming the Frequency and Period
- •10.5 Programming the Duty Cycle
- •10.5.1 Sample Calculations
- •10.5.2 Reading the Current Value of the Down-counter
- •10.5.3 Enabling the PWM Outputs
- •10.5.4 Generating Analog Outputs
- •11.1 EPA Functional Overview
- •11.2 EPA and Timer/Counter Signals and Registers
- •11.3 Timer/Counter Functional Overview
- •11.3.1 Timer Multiplexing on the Time Bus
- •11.4 EPA Channel Functional Overview
- •11.4.1 Operating in Input Capture Mode
- •11.4.2 Operating in Output Compare Mode
- •11.4.3 Operating in Compare Mode with the Output/Simulcapture Channels
- •11.4.4 Generating a 32-bit Time Value
- •11.4.5 Controlling a Pair of Adjacent Pins
- •11.5 Programming the EPA and Timer/Counters
- •11.5.1 Configuring the EPA and Timer/Counter Signals
- •11.5.2 Programming the Timers
- •11.5.3 Programming the Capture/Compare Channels
- •11.5.4 Programming the Compare-only (Output/Simulcapture) Channels
- •11.6 Enabling the EPA Interrupts
- •11.7 Determining Event Status
- •CHAPTER 12 Analog-to-digital (A/D) Converter
- •12.1 A/D Converter Functional Overview
- •12.2 A/D Converter Signals and Registers
- •12.3 A/D Converter Operation
- •12.4 Programming the A/D Converter
- •12.4.1 Programming the A/D Test Register
- •12.4.2 Programming the A/D Result Register (for Threshold Detection Only)
- •12.4.3 Programming the A/D Time Register
- •12.4.4 Programming the A/D Command Register
- •12.4.5 Programming the A/D Scan Register
- •12.4.6 Enabling the A/D Interrupt
- •12.5 Determining A/D Status and Conversion Results
- •12.6 Design Considerations
- •12.6.1 Designing External Interface Circuitry
- •12.6.1.1 Minimizing the Effect of High Input Source Resistance
- •12.6.1.2 Suggested A/D Input Circuit
- •12.6.1.3 Analog Ground and Reference Voltages
- •12.6.2 Understanding A/D Conversion Errors
- •CHAPTER 13 Minimum Hardware Considerations
- •13.1 Minimum Connections
- •13.1.1 Unused Inputs
- •13.1.2 I/O Port Pin Connections
- •13.2 Applying and Removing Power
- •13.3 Noise Protection Tips
- •13.4 The On-chip Oscillator Circuitry
- •13.5 Using an External Clock Source
- •13.6 Resetting the Microcontroller
- •13.6.1 Generating an External Reset
- •13.6.2 Issuing the Reset (RST) Instruction
- •13.6.3 Issuing an Illegal IDLPD Key Operand
- •13.6.4 Enabling the Watchdog Timer
- •13.6.5 Detecting Clock Failure
- •13.7 Identifying the Reset Source
- •14.1 Special Operating Mode Signals and Registers
- •14.2 Reducing Power Consumption
- •14.3 Idle Mode
- •14.3.1 Enabling and Disabling Idle Mode
- •14.3.2 Entering and Exiting Idle Mode
- •14.4 Powerdown Mode
- •14.4.1 Enabling and Disabling Powerdown Mode
- •14.4.2 Entering Powerdown Mode
- •14.4.3 Exiting Powerdown Mode
- •14.4.3.1 Generating a Hardware Reset
- •14.4.3.2 Asserting the External Interrupt Signal
- •14.4.3.3 Selecting an External Capacitor
- •14.5 ONCE Mode
- •CHAPTER 15 Interfacing with External Memory
- •15.1 Internal and External Addresses
- •15.2 External Memory Interface Signals and Registers
- •15.3 The Chip-select Unit
- •15.3.1 Defining Chip-select Address Ranges
- •15.3.2 Controlling Bus Parameters
- •15.3.3 Chip-select Unit Initial Conditions
- •15.3.4 Programming the Chip-select Registers
- •15.3.5 Example of a Chip-select Setup
- •15.4 Chip Configuration Registers and Chip Configuration Bytes
- •15.5 Bus Width and Multiplexing
- •15.5.1 A 16-bit Example System
- •15.5.2 16-bit Bus Timings
- •15.5.3 8-bit Bus Timings
- •15.5.4 Comparison of Multiplexed and Demultiplexed Buses
- •15.6 Wait States (Ready Control)
- •15.7 Bus-hold Protocol
- •15.7.1 Enabling the Bus-hold Protocol
- •15.7.2 Disabling the Bus-hold Protocol
- •15.7.3 Hold Latency
- •15.7.4 Regaining Bus Control
- •15.8 Write-control Modes
- •15.9 System Bus AC Timing Specifications
- •15.9.1 Deferred Bus-cycle Mode
- •15.9.2 Explanation of AC Symbols
- •15.9.3 AC Timing Definitions
- •16.1 Serial Debug Unit (SDU) Functional Overview
- •16.2 SDU Signals and Registers
- •16.3 SDU Operation
- •16.3.1 SDU State Machine
- •16.3.2 Code RAM Access State Machine
- •16.3.3 Minimizing Latency
- •16.4 Code RAM Access
- •16.4.1 Code RAM Data Transfer
- •16.4.2 Code RAM Access Instructions
- •16.4.3 Code RAM Data Transfer Example
- •16.5 SDU Interface Connector
- •17.1 Signals and Registers
- •17.2 Memory Protection Options
- •17.3 Entering Test-ROM Routines
- •17.3.1 Power-up and Power-down Sequences
- •17.4 ROM-dump Routine and Circuit
- •17.5 Serial Port Mode Routine
- •17.5.1 Serial Port RISM
- •17.5.2 Serial Port Mode Circuit
- •17.6 SDU RISM Execution Routine
- •17.6.1 SDU RISM Data Transfer
- •17.6.1.1 SDU RISM Data Transfer Before
- •17.6.1.2 SDU RISM Data Transfer After
- •17.6.2 SDU RISM Execution Circuit
- •17.7 RISM Command Descriptions
- •17.8 Executing Programs from Register RAM
- •17.9 RISM Command Examples
- •17.9.1 Serial Port Mode RISM Read Command Example
- •17.9.2 Serial Port Mode RISM Write Command Example
- •17.9.3 SDU RISM Execution Write Command Example
- •17.9.4 SDU RISM Execution Go Command Example
- •B.1 Functional Groupings of Signals
- •B.2 Signal Descriptions
- •B.3 Default Conditions
CHAPTER 8
SERIAL I/O (SIO) PORT
A serial input/output (SIO) port provides a means for the system to communicate with external devices. This microcontroller has a two-channel serial I/O (SIO) port that shares pins with port 2. This chapter describes the SIO port and explains how to configure it.
8.1SERIAL I/O (SIO) PORT FUNCTIONAL OVERVIEW
The serial I/O port is an asynchronous/synchronous port that has two identical channels. Each channel includes a universal asynchronous receiver and transmitter (UART) and has four modes of operation: one synchronous mode (mode 0) and three asynchronous modes (modes 1, 2, and 3). Each channel consists of a dedicated receiver, transmitter, control logic, two interrupt signals, and a baud-rate generator.
The transmitter and receiver contain buffers and shift registers. The buffers are accessible as spe- cial-function registers (SFRs). Write transmit data to the transmit buffer (SBUFx_TX) and read received data from the receive buffer (SBUFx_RX). Unlike the buffers, the shift registers are internal registers and are not accessible as SFRs. For receptions, data is shifted into the receive shift register, least-significant bit first, via the receive data pin (RXDx). After the last bit (eighth bit for mode 0 or stop bit for modes 1, 2, and 3) is shifted in, the receiver transfers the data from the receive shift register to SBUFx_RX where it can be accessed. For transmissions, data in SBUFx_TX is transferred to the transmit shift register then shifted out through the serial transmit pin (RXDx for mode 0 or TXDx for modes 1, 2, and 3).
Each channel contains a serial port control (SPx_CON) register and a serial port status (SPx_STATUS) register. SPx_CON configures the SIO channel for one of the operating modes and for receptions or transmissions. SPx_STATUS contains status and error flags. These registers are discussed in detail in “Programming the Control Register” on page 8-11 and “Determining Serial Port Status” on page 8-16.
Each SIO channel has two interrupt signals, allowing for interrupt-driven transmit and receive service routines. The receive interrupt (RIx) indicates the receive buffer (SBUFx_RX) contains received data, available for reading. The transmit interrupt (TIx) indicates the transmit buffer (SBUFx_TX) is empty and available for writing.
Each channel contains a 15-bit baud-rate generator. Either the internal peripheral clock or a signal input on the T2CLK pin can provide the clock signal. The baud-rate register (SP x_BAUD) selects the clock source and the baud rate. For synchronous mode 0, the baud-rate generator controls the baud rate output on the serial clock pin (TXDx). For asynchronous modes 1, 2, and 3, the baudrate generator controls the transmit and receive shift clocks.
8-1
8XC196EA USER’S MANUAL
The SIO channel signals, registers, and interrupts are shown in Figures 8-1 and 8-2. The signals and registers are described in the following section.
Internal Bus
SP_BAUD.15
T2CLK 0 f 1
Receiver |
|
Receive Shift Reg |
Receive |
|
RXD (data)
Transmit Input for receptions
Output for transmissions
SBUF_RX
SP_CON.3
Transmitter
Transmit Shift Reg
SBUF_TX |
|
Control Logic |
|
SP_CON |
TI Interrupt |
|
|
SP_STATUS |
RI Interrupt |
Baud-rate
Generator
TXD (clock)
SP_BAUD
A5104-01
Figure 8-1. SIO Block Diagram (Mode 0)
As shown in Figure 8-1, the RXDx pin is the data pin and the TXDx pin is the clock pin for synchronous mode 0 operation. In this mode, the baud-rate generator drives eight pulses out the TXDx pin and the UART shifts data, least-significant bit first, into or out of the microcontroller via the RXDx pin. The UART samples data when the TXDx pulse is low. “Synchronous Mode (Mode 0)” on page 8-6 describes mode 0 in detail.
8-2
SERIAL I/O (SIO) PORT
Internal Bus
SP_BAUD.15
T2CLK 0 f 1
Receiver
Receive Shift Reg
SBUF_RX
Transmitter
Transmit Shift Reg
SBUF_TX
Control Logic
SP_CON
SP_STATUS
Baud-rate
Generator
SP_BAUD
RXD
(data receptions)
TXD
(data transmissions)
TI Interrupt
RI Interrupt
A5105-01
Figure 8-2. SIO Block Diagram (Modes 1, 2, and 3)
As shown in Figure 8-2, the RXDx pin is the receive data pin and the TXDx pin is the transmit data pin for asynchronous modes 1, 2, and 3. Either the internal operating frequency (f) or an input signal on the T2CLK pin provides the clock input to the baud-rate generator. “Asynchronous Modes (Modes 1, 2, and 3)” on page 8-7 describes modes 1, 2, and 3 in detail.
8-3
8XC196EA USER’S MANUAL
8.2SERIAL I/O PORT SIGNALS AND REGISTERS
Table 8-1 describes the SIO signals and Table 8-2 describes the control and status registers.
Table 8-1. Serial Port Signals
Serial Port |
Serial |
|
|
Port |
Description |
||
Signal |
Signal |
||
|
|||
|
Type |
|
|
|
|
|
|
RXD |
I/O |
Receive Serial Data 0 and 1 |
|
|
|
In modes 1, 2, and 3, RXD0 and 1 receive serial port input data. In mode 0, |
|
|
|
they function as either inputs or open-drain outputs for data. |
|
|
|
RXD0 shares a package pin with P2.1, and RXD1 shares a package pin |
|
|
|
with P2.4. |
|
|
|
|
|
T2CLK |
I |
Timer 2 Clock |
|
|
|
The internal operating freakiness (f) or an input signal on T2CLK provides |
|
|
|
the clock source for the baud-rate generator. Clearing SPx_BAUD.15 |
|
|
|
selects T2CLK as the clock source. |
|
|
|
T2CLK shares a package pin with P7.2. |
|
|
|
|
|
TXD |
O |
Transmit Serial Data 0 and 1 |
|
|
|
In serial I/O modes 1, 2, and 3, TXD0 and 1 transmit serial port output |
|
|
|
data. In mode 0, they are the serial clock output. |
|
|
|
TXD0 shares a package pin with P2.0 and TXD1 shares a package pin |
|
|
|
with P2.3. |
|
|
|
|
Table 8-2. Serial Port Control and Status Registers
Mnemonic |
Address |
Description |
|
|
|
INT_MASK |
0008H |
Interrupt Mask |
|
|
Setting the TIx bit enables the transmit interrupt; clearing the bit |
|
|
disables (masks) the interrupt. |
|
|
Setting the RIx bit enables the receive interrupt; clearing the bit |
|
|
disables (masks) the interrupt. |
|
|
|
INT_PEND |
0009H |
Interrupt Pending |
|
|
When set, the TIx bit indicates a pending transmit interrupt. |
|
|
When set, the RIx bit indicates a pending receive interrupt. |
|
|
|
P2_DIR |
1FD2H |
Port Direction Register |
P7_DIR |
1FCAH |
Each bit controls the configuration of the corresponding pin. |
|
|
|
|
|
Clearing a bit configures the corresponding pin as a complementary |
|
|
output; setting a bit configures the corresponding pin as an open- |
|
|
drain output or a high-impedance input. |
|
|
Write to P2_DIR.1, P2_DIR.4, P7_DIR.2, P2_DIR.0 and P7_DIR.2 |
|
|
to configure RXD0, RXD1, T2CLK, TXD0, and TXD1. (See “Config- |
|
|
uring the Serial Port Pins” on page 8-10.) |
|
|
|
8-4
SERIAL I/O (SIO) PORT
Table 8-2. Serial Port Control and Status Registers (Continued)
Mnemonic |
Address |
Description |
|
|
|
P2_MODE |
1FD0H |
Port Mode Register |
P7_MODE |
1FC8H |
Each bit controls the mode of the corresponding pin. Setting a bit |
|
|
|
|
|
configures a pin as a special-function signal; clearing a bit |
|
|
configures a pin as a general-purpose I/O signal. |
|
|
Set P2_MODE.1, P2_MODE.4, P7_MODE.2, P2_MODE.0 and |
|
|
P7_MODE.2 to configure pins P2.1, P2.4, P7.2, and P2.0 as RXD0, |
|
|
RXD1, T2CLK, TXD0, and TXD1. (See “Configuring the Serial Port |
|
|
Pins” on page 8-10.) |
|
|
|
P2_PIN |
1FD6H |
Port Pin Register |
P7_PIN |
1FCEH |
Each bit reflects the current state of the corresponding pin, |
|
|
|
|
|
regardless of the pin’s mode and configuration. |
|
|
|
P2_REG |
1FD4H |
Port Data Output Register |
P7_REG |
1FCCH |
For I/O Mode (Px_MODE.x = 0) |
|
|
|
|
|
When a port pin is configured as a complementary output |
|
|
(Px_DIR.x = 0), setting the corresponding port data bit drives a |
|
|
one on the pin, and clearing the corresponding port data bit |
|
|
drives a zero on the pin. |
|
|
When a port pin is configured as a high-impedance input or an |
|
|
open-drain output (Px_DIR.x = 1), clearing the corresponding |
|
|
port data bit drives a zero on the pin, and setting the corre- |
|
|
sponding port data bit floats the pin, making it available as a |
|
|
high-impedance input. |
|
|
For Special-function Mode (Px_MODE.x = 1) |
|
|
When a port pin is configured as an output (either comple- |
|
|
mentary or open-drain), the corresponding port data bit value is |
|
|
immaterial because the corresponding on-chip peripheral or |
|
|
system function controls the pin. |
|
|
To configure a pin as a high-impedance input, set both the |
|
|
Px_DIR and Px_REG bits. |
|
|
Write to P2_REG.1, P2_REG.4, P7_REG.2, P2_REG.0 and |
|
|
P7_REG.2 to configure RXD0, RXD1, T2CLK, TXD0, and TXD1. |
|
|
(See “Configuring the Serial Port Pins” on page 8-10.) |
|
|
|
SBUF0_RX |
1F88H |
Serial Port x Receive Buffer |
SBUF1_RX |
1F98H |
This register contains data received from the RXDx pin. |
|
|
|
|
|
|
SBUF0_TX |
1F8AH |
Serial Port x Transmit Buffer |
SBUF1_TX |
1F9AH |
This register contains data that is ready for transmission. In modes |
|
|
|
|
|
1, 2, and 3, writing to SBUFx_TX starts a transmission. In mode 0, |
|
|
writing to SBUFx_TX starts a transmission only if the receiver is |
|
|
disabled (SPx_CON.3 = 0). |
|
|
|
SP0_BAUD |
1F8CH, 1F8DH |
Serial Port x Baud Rate |
SP1_BAUD |
1F9CH, 1F8DH |
This register selects the serial port baud rate and clock source. The |
|
|
|
|
|
most-significant bit selects the clock source. The lower 15 bits |
|
|
represent the baud value, an unsigned integer that determines the |
|
|
baud rate. |
|
|
|
8-5