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CHAPTER 8

SERIAL I/O (SIO) PORT

A serial input/output (SIO) port provides a means for the system to communicate with external devices. This microcontroller has a two-channel serial I/O (SIO) port that shares pins with port 2. This chapter describes the SIO port and explains how to configure it.

8.1SERIAL I/O (SIO) PORT FUNCTIONAL OVERVIEW

The serial I/O port is an asynchronous/synchronous port that has two identical channels. Each channel includes a universal asynchronous receiver and transmitter (UART) and has four modes of operation: one synchronous mode (mode 0) and three asynchronous modes (modes 1, 2, and 3). Each channel consists of a dedicated receiver, transmitter, control logic, two interrupt signals, and a baud-rate generator.

The transmitter and receiver contain buffers and shift registers. The buffers are accessible as spe- cial-function registers (SFRs). Write transmit data to the transmit buffer (SBUFx_TX) and read received data from the receive buffer (SBUFx_RX). Unlike the buffers, the shift registers are internal registers and are not accessible as SFRs. For receptions, data is shifted into the receive shift register, least-significant bit first, via the receive data pin (RXDx). After the last bit (eighth bit for mode 0 or stop bit for modes 1, 2, and 3) is shifted in, the receiver transfers the data from the receive shift register to SBUFx_RX where it can be accessed. For transmissions, data in SBUFx_TX is transferred to the transmit shift register then shifted out through the serial transmit pin (RXDx for mode 0 or TXDx for modes 1, 2, and 3).

Each channel contains a serial port control (SPx_CON) register and a serial port status (SPx_STATUS) register. SPx_CON configures the SIO channel for one of the operating modes and for receptions or transmissions. SPx_STATUS contains status and error flags. These registers are discussed in detail in “Programming the Control Register” on page 8-11 and “Determining Serial Port Status” on page 8-16.

Each SIO channel has two interrupt signals, allowing for interrupt-driven transmit and receive service routines. The receive interrupt (RIx) indicates the receive buffer (SBUFx_RX) contains received data, available for reading. The transmit interrupt (TIx) indicates the transmit buffer (SBUFx_TX) is empty and available for writing.

Each channel contains a 15-bit baud-rate generator. Either the internal peripheral clock or a signal input on the T2CLK pin can provide the clock signal. The baud-rate register (SP x_BAUD) selects the clock source and the baud rate. For synchronous mode 0, the baud-rate generator controls the baud rate output on the serial clock pin (TXDx). For asynchronous modes 1, 2, and 3, the baudrate generator controls the transmit and receive shift clocks.

8-1

8XC196EA USER’S MANUAL

The SIO channel signals, registers, and interrupts are shown in Figures 8-1 and 8-2. The signals and registers are described in the following section.

Internal Bus

SP_BAUD.15

T2CLK 0 f 1

Receiver

 

Receive Shift Reg

Receive

 

RXD (data)

Transmit Input for receptions

Output for transmissions

SBUF_RX

SP_CON.3

Transmitter

Transmit Shift Reg

SBUF_TX

 

Control Logic

 

SP_CON

TI Interrupt

 

SP_STATUS

RI Interrupt

Baud-rate

Generator

TXD (clock)

SP_BAUD

A5104-01

Figure 8-1. SIO Block Diagram (Mode 0)

As shown in Figure 8-1, the RXDx pin is the data pin and the TXDx pin is the clock pin for synchronous mode 0 operation. In this mode, the baud-rate generator drives eight pulses out the TXDx pin and the UART shifts data, least-significant bit first, into or out of the microcontroller via the RXDx pin. The UART samples data when the TXDx pulse is low. “Synchronous Mode (Mode 0)” on page 8-6 describes mode 0 in detail.

8-2

SERIAL I/O (SIO) PORT

Internal Bus

SP_BAUD.15

T2CLK 0 f 1

Receiver

Receive Shift Reg

SBUF_RX

Transmitter

Transmit Shift Reg

SBUF_TX

Control Logic

SP_CON

SP_STATUS

Baud-rate

Generator

SP_BAUD

RXD

(data receptions)

TXD

(data transmissions)

TI Interrupt

RI Interrupt

A5105-01

Figure 8-2. SIO Block Diagram (Modes 1, 2, and 3)

As shown in Figure 8-2, the RXDx pin is the receive data pin and the TXDx pin is the transmit data pin for asynchronous modes 1, 2, and 3. Either the internal operating frequency (f) or an input signal on the T2CLK pin provides the clock input to the baud-rate generator. “Asynchronous Modes (Modes 1, 2, and 3)” on page 8-7 describes modes 1, 2, and 3 in detail.

8-3

8XC196EA USER’S MANUAL

8.2SERIAL I/O PORT SIGNALS AND REGISTERS

Table 8-1 describes the SIO signals and Table 8-2 describes the control and status registers.

Table 8-1. Serial Port Signals

Serial Port

Serial

 

Port

Description

Signal

Signal

 

 

Type

 

 

 

 

RXD

I/O

Receive Serial Data 0 and 1

 

 

In modes 1, 2, and 3, RXD0 and 1 receive serial port input data. In mode 0,

 

 

they function as either inputs or open-drain outputs for data.

 

 

RXD0 shares a package pin with P2.1, and RXD1 shares a package pin

 

 

with P2.4.

 

 

 

T2CLK

I

Timer 2 Clock

 

 

The internal operating freakiness (f) or an input signal on T2CLK provides

 

 

the clock source for the baud-rate generator. Clearing SPx_BAUD.15

 

 

selects T2CLK as the clock source.

 

 

T2CLK shares a package pin with P7.2.

 

 

 

TXD

O

Transmit Serial Data 0 and 1

 

 

In serial I/O modes 1, 2, and 3, TXD0 and 1 transmit serial port output

 

 

data. In mode 0, they are the serial clock output.

 

 

TXD0 shares a package pin with P2.0 and TXD1 shares a package pin

 

 

with P2.3.

 

 

 

Table 8-2. Serial Port Control and Status Registers

Mnemonic

Address

Description

 

 

 

INT_MASK

0008H

Interrupt Mask

 

 

Setting the TIx bit enables the transmit interrupt; clearing the bit

 

 

disables (masks) the interrupt.

 

 

Setting the RIx bit enables the receive interrupt; clearing the bit

 

 

disables (masks) the interrupt.

 

 

 

INT_PEND

0009H

Interrupt Pending

 

 

When set, the TIx bit indicates a pending transmit interrupt.

 

 

When set, the RIx bit indicates a pending receive interrupt.

 

 

 

P2_DIR

1FD2H

Port Direction Register

P7_DIR

1FCAH

Each bit controls the configuration of the corresponding pin.

 

 

 

 

Clearing a bit configures the corresponding pin as a complementary

 

 

output; setting a bit configures the corresponding pin as an open-

 

 

drain output or a high-impedance input.

 

 

Write to P2_DIR.1, P2_DIR.4, P7_DIR.2, P2_DIR.0 and P7_DIR.2

 

 

to configure RXD0, RXD1, T2CLK, TXD0, and TXD1. (See “Config-

 

 

uring the Serial Port Pins” on page 8-10.)

 

 

 

8-4

SERIAL I/O (SIO) PORT

Table 8-2. Serial Port Control and Status Registers (Continued)

Mnemonic

Address

Description

 

 

 

P2_MODE

1FD0H

Port Mode Register

P7_MODE

1FC8H

Each bit controls the mode of the corresponding pin. Setting a bit

 

 

 

 

configures a pin as a special-function signal; clearing a bit

 

 

configures a pin as a general-purpose I/O signal.

 

 

Set P2_MODE.1, P2_MODE.4, P7_MODE.2, P2_MODE.0 and

 

 

P7_MODE.2 to configure pins P2.1, P2.4, P7.2, and P2.0 as RXD0,

 

 

RXD1, T2CLK, TXD0, and TXD1. (See “Configuring the Serial Port

 

 

Pins” on page 8-10.)

 

 

 

P2_PIN

1FD6H

Port Pin Register

P7_PIN

1FCEH

Each bit reflects the current state of the corresponding pin,

 

 

 

 

regardless of the pin’s mode and configuration.

 

 

 

P2_REG

1FD4H

Port Data Output Register

P7_REG

1FCCH

For I/O Mode (Px_MODE.x = 0)

 

 

 

 

When a port pin is configured as a complementary output

 

 

(Px_DIR.x = 0), setting the corresponding port data bit drives a

 

 

one on the pin, and clearing the corresponding port data bit

 

 

drives a zero on the pin.

 

 

When a port pin is configured as a high-impedance input or an

 

 

open-drain output (Px_DIR.x = 1), clearing the corresponding

 

 

port data bit drives a zero on the pin, and setting the corre-

 

 

sponding port data bit floats the pin, making it available as a

 

 

high-impedance input.

 

 

For Special-function Mode (Px_MODE.x = 1)

 

 

When a port pin is configured as an output (either comple-

 

 

mentary or open-drain), the corresponding port data bit value is

 

 

immaterial because the corresponding on-chip peripheral or

 

 

system function controls the pin.

 

 

To configure a pin as a high-impedance input, set both the

 

 

Px_DIR and Px_REG bits.

 

 

Write to P2_REG.1, P2_REG.4, P7_REG.2, P2_REG.0 and

 

 

P7_REG.2 to configure RXD0, RXD1, T2CLK, TXD0, and TXD1.

 

 

(See “Configuring the Serial Port Pins” on page 8-10.)

 

 

 

SBUF0_RX

1F88H

Serial Port x Receive Buffer

SBUF1_RX

1F98H

This register contains data received from the RXDx pin.

 

 

 

 

 

SBUF0_TX

1F8AH

Serial Port x Transmit Buffer

SBUF1_TX

1F9AH

This register contains data that is ready for transmission. In modes

 

 

 

 

1, 2, and 3, writing to SBUFx_TX starts a transmission. In mode 0,

 

 

writing to SBUFx_TX starts a transmission only if the receiver is

 

 

disabled (SPx_CON.3 = 0).

 

 

 

SP0_BAUD

1F8CH, 1F8DH

Serial Port x Baud Rate

SP1_BAUD

1F9CH, 1F8DH

This register selects the serial port baud rate and clock source. The

 

 

 

 

most-significant bit selects the clock source. The lower 15 bits

 

 

represent the baud value, an unsigned integer that determines the

 

 

baud rate.

 

 

 

8-5

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