EVENT PROCESSOR ARRAY (EPA)
OSx_TIME |
Address: |
See Table 11-2 on page 11-4 |
x = 0–7 |
Reset: |
XXXXH |
The output/simulcapture time registers (OSx_TIME) are the event-time registers for the output/simulcapture channels. The EPA triggers a compare event when the reference timer matches the value in OSx_TIME. If simulcapture is enabled, the EPA simultaneously captures the value of the specified timer into this register, overwriting the previous value.
15 |
0 |
OS Timer Value
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15:0 |
OS Timer Value |
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After programming the OSx_CON register, write the compare event time to this register. |
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The EPA generates the programmed event when the value of the reference timer |
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matches the event-time value in this register. |
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If simulcapture is enabled, the EPA simultaneously captures the value of the specified |
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timer into this register, overwriting the event-time value. |
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Figure 11-17. Output Simulcapture x Time (OSx_TIME) Register |
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11.6 ENABLING THE EPA INTERRUPTS
The EPA generates 32 individual event interrupts (EPA16:0, OS7:0, OVRTM4:1, OVR2:0) and the shared overrun event interrupt (EPAx_OVR) from EPA16:3. The individual interrupts are directly mapped into the two peripheral interrupt handler (PIH) interrupt pending registers (PIH0_INT_PEND and PIH1_INT_PEND). The timer overrun events from EPA16:3 share the EPAx_OVR interrupt, which maps into the INT_PEND register. To enable the individual interrupts, set the corresponding bits in the PIHx_INT_MASK registers, then set the appropriate bits in INT_MASK1 to enable either PTS or interrupt controller service for the PIH vectors. To enable the shared overrun interrupt, set the corresponding bit in the INT_MASK register. Chapter 6, “Standard and PTS Interrupts,” discusses the interrupts in greater detail.
11-25
8XC196EA USER’S MANUAL
INT_MASK1 |
Address: |
0013H |
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Reset State: |
00H |
The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can be read from or written to as a byte register. PUSHA saves this register on the stack and POPA restores it.
7 |
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0 |
NMI |
STACK |
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PIH0_PTS |
PIH0_INT |
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PIH1_PTS |
PIH1_INT |
SSIO1 |
SSIO0 |
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7:0 |
Setting a bit enables the corresponding interrupt. |
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Bit Mnemonic Interrupt Description |
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NMI† |
Nonmaskable Interrupt |
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STACK† |
Stack Overflow Error |
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PIH0_PTS |
PIH0 PTS Service Request |
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PIH0_INT |
PIH0 Interrupt Request |
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PIH1_PTS |
PIH1 PTS Service Request |
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PIH1_INT |
PIH1 Interrupt Request |
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SSIO1 |
SSIO1 Transfer |
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SSIO0 |
SSIO0 Transfer |
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† The NMI and stack overflow interrupts are always enabled. These nonfunctional mask |
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bits exist for design symmetry with the INT_PEND1 register. Always write zeros to these |
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bits. |
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Figure 11-21. Interrupt Mask 1 (INT_MASK1) Register
11.7 DETERMINING EVENT STATUS
In compare mode, an interrupt pending bit is set each time a match occurs on an enabled event (even if the interrupt is specifically masked in the mask register). In capture mode, an interrupt pending bit is set each time a programmed event is captured and the event time moves from the capture buffer to the EPAx_TIME register. If the capture buffer is full when an event occurs, an overrun interrupt pending bit is set.
Even if an interrupt is masked, software can poll the interrupt pending registers to determine whether an event has occurred.
11-28
12
Analog-to-digital
(A/D) Converter