Ir drop (power grid design)

Resistance in the power and ground distribution network causes IR drop. Nanometer designs are extremely susceptible to IR drop because power and ground wire resistivity increases with decreasing geometries, while the overall power supply voltage decreases. Gate delays increase non-linearly as voltage at gates decrease. The result is poor performance and increased noise susceptibility. Furthermore, gates with different voltage levels communicating with each other across the chip can propagate erroneous data, causing a malfunction. The power grid must be robust enough to prevent reliability problems from EM effects without costly over-design. In nanometer design, it is essential to understand power issues early in the design cycle, and in detail, to minimize power consumption and to address considerations such as temperature, leakage, return path, etc.

CROSSTALK AND INDUCTANCE

When signals in neighboring wires transition, the coupling capacitance between the wires can cause crosstalk. The amount of crosstalk depends on the mutual capacitance between the wires and the signal slew (i.e., the switching speed). Crosstalk causes noise problems when a transition on a fast aggressor wire causes a glitch to appear on a victim wire. The situation is more complex when simultaneous switching occurs on both wires. This situation can create crosstalk-induced delay changes which speed up or slow down signals depending on their phase relationship. Inductance between the wires can exacerbate crosstalk. Coupling capacitance and inductance effects increase with decreasing process geometries, which will make it important to account for these effects on crosstalk generation. Beyond 90 nm, it will become important to account for an increasing number of inductive effects, such as power rail “ringing” due to the simultaneous switching of multiple gates.

ELECTROMIGRATION

Electromigration occurs when the current per cross-sectional area in a wire or via is too high. In power and ground wires, a current-induced “electron wind” causes metal ions to migrate, creating voids “upwind” and metal-ion accumulation “downwind” in the form of “hillocks” and “whiskers.” Voids can also cause open circuits or increase wire resistance, which in turn increases delays and noise susceptibility. Hillocks and whiskers can cause short circuits to neighboring wires. EM is increasingly a signal wire issue as well. Wire self-heat (Joule heating) occurs when the dynamic current density is too high, resulting in EM.

DIGITAL-ANALOG INTEGRATION

Approximately 50 % of SoCs at 0.13 micron include critical analog/mixed-signal circuitry, and the percentage will increase in nanometer design. Making these sophisticated analog functions work at all, much less while sharing a

chip with a number of large digital systems, is a huge design challenge. Although the analog circuitry often accounts for only a small percent of the transistors, it accounts for 20 percent of the area, 40 percent of the design effort, and 50 percent of the respins. Nanometer digital/mixed-signal (D/MS) designs require new design approaches to optimize the chip’s overall performance and its yield. For more information regarding digital-analog convergence, see the Cadence Digital-Analog Convergence Executive Technology Brief.

POWER CONSUMPTION

Power consumption is an issue for a growing number of applications, from prolonging battery life in mobile equipment to minimizing package costs and cooling noise in stationary applications. Concerns with power consumption and the concomitant implications for temperature and reliability lead to multivoltage ICs. Other power-related issues include clocking structure design and leakage current, which increase the risk of signal integrity issues and place additional demands on ensuring electrical correctness. Since power consumption is directly related to wiring capacitance, power minimization requires careful wiring optimization and power distribution across the chip. Nanometer design tools must have the ability to cope with complex clocking schemes, multi-voltage blocks, leakage minimization, etc.

SYSTEM SIGNAL TRANSMISSION

Without effective IC packaging and timely design-in by system design teams, even the best silicon will fail in the market. High density pinouts require elaborate custom packaging, which can cost as much as the silicon itself. Ineffective chip I/O placement results can lead to silicon underutilization or even signals that are not routable. High frequency and sensitive analog/RF signals require careful, prioritized routing through the chip, package, and board. Analyzing system-level signal performance and integrity from die to die – through IC packages and across the board – is essential. Addressing system signal transmission issues is especially difficult since different design teams at different companies are often responsible for each element. For more information regarding system signal transmission, see the Cadence Silicon-Package-Board Convergence Executive Technology Brief.

MANUFACTURING RULES

Manufacturing processes using copper wiring, chemical-mechanical polishing (CMP), and subwavelength lithography lead to exceedingly complex and arcane design rules. Antenna rules, for example, require careful handling to avoid via proliferation and to minimize wire lengths. In order to minimize ramp-up time, foundries continue to change the rules until long after the introduction of a new process, and the situation is worsening with each new process node.

Nanometer routers must explicitly provide for variable width and variable spacing and must be capable of adapting to the requirements of copper wires, multiple vias, optical proximity correction (OPC), phase-shift masks (PSM), and CMP processes.

YIELD OPTIMIZATION

More than 50% of SoCs end up in high-volume applications. As processes get smaller, process variability grows. Designing for the “worst case” becomes impractically conservative, and design-centering techniques must replace the use of process corners. At nanometer levels, intra-chip variances raise a whole new level of issues. Exotic nanometer process requirements and increasingly intractable optical lithography challenges make yield management a major design issue, not simply a manufacturing issue.