5. Signal integrity closure

Class Activity

ACTIVITY 1

Introduction TEXT 1A:

Task 109. Read the passage and guess what the text is about.

For nanometer designs it is no longer sufficient to just achieve timing closure – a design must also reach signal integrity (SI) closure. SI closure implies that the design is free from SI-related functional problems and meets its timing goals while accounting for the impact of SI (see Figure 19).

Figure 19: SI closure criteria

In the pre-nanometer design era, SI effects were either ignored or analyzed and manually repaired after achieving timing closure. This approach no longer works for nanometer designs because the number of potential SI violations exceeds what can be easily managed in a post-route analyze and repair methodology. The increase in SI problems arises from a number of technology advances including reduced feature sizes, decreases in interconnect pitch, and lower power supply voltages. With each new generation of process technology there is a dramatic increase in onchip crosstalk noise due to both the increase in the number of wires with a large percentage of coupling capacitance, as shown in Figure 20, and the accompanying rise in clock frequencies.

Figure 20: Percentage of nets versus coupling-cap/total-cap for 150 nm, 130 nm

For nanometer designs, SI closure must be managed simultaneously with timing closure. To achieve SI closure a design will need to undergo a number of concurrent optimization steps that prevent, analyze, and repair SI-induced problems. Each phase of the design implementation can be subject to these steps including placement, clock tree synthesis, and final detailed routing.

In applying SI optimizations a number of factors must be considered including the precision of the design data available at each stage of the design process. For example, during physical synthesis, SI optimization based on analysis of estimated routes is misleading as there is not enough wire information available to make the correct choices. Without knowing the wire track assignments and layers it is impossible to predict crosstalk effects. What is required is an implementation solution that continuously converges towards SI closure through increasing model

refinement and the appropriate amount of optimization for the given design phase. The solution must be flexible to permit different design trade-offs for different end market needs and it must be efficient without adding significant design overhead.

Task 110. Organizing your thoughts:

1. What does SI closure imply?

2. Why does the approach of the pre-nanometer design era no longer work for nanometer designs?

3. What does the increase in SI problems arise from?

4. In what way must SI closure be managed for nanometer designs?

5. What factors must be considered in applying SI optimizations?

Task 111. Study the sentences with the following words and word combinations:

Intellectual property (IP) blocks – блоки интеллектуальной собственности

I/Os – input/output (s) – ввод-вывод; обмен данными; устройства ввода вывода

Coupling capacitance – переходная емкость

Grounded capacitance – емкость относительно земли

Repeaters – ретрансляторы; промежуточные усилители (линии связи); линейные трансформаторы (в телефонии)

Noise-sensitive blocks – блоки чувствительные к шумам

SI closure – нарушение целостности сигналов

Routing layers – уровни трассировки

Digital cores – цифровые ядра

Analog cores – аналоговые ядра

Noise source – источник шума

Guard-ring – защитное (охранное) кольцо (транзистора в ИС)

Task 112. Read the text carefully paying attention to the italicized words and word combinations and try to understand its contents:

BASIC TEXT 1B:

SI CLOSURE METHODOLOGY

In order to efficiently achieve SI closure certain design methodology decisions should be made up front. They should be based on product schedule and market requirements. SI avoidance is the most efficient way to achieve SI closure, but it needs to be balanced against trade-offs of other design metrics such as area, performance, and power. For example, most SI problems can be avoided by spreading wires farther apart and reducing the ratio of coupling capacitance to grounded capacitance. However, if this approach is applied everywhere in the design the result is a much larger die and increased cost. For certain critical nets, such as clocks or chip-level buses, a practical solution could involve using wider wires, shielding with power and ground lines, using repeaters to break up wire lengths, using different routing layers for adjacent wires, or using 2-3X minimum spacing.

Other up-front decisions can be based around the selection of intellectual property (IP) blocks. Ideally IP blocks should neither be noise-sensitive or noise sources. This applies to all forms of IP from standard cells, memories, I/Os, and custom digital or analog cores. If an IP block is noise-sensitive or a noise source, then early decisions can be made to protect this block – such as using guard-rings, applying blockages to prevent over-the-block or near-block routing, spacing, or shielding, or even selecting an alternative implementation of the same function.

All of the SI methodology choices mentioned above can be made early in the design process. They all involve trade-offs in terms of area, performance, and engineering schedule. They can be implemented as design methodology restrictions and the implementation tools can be used to enforce the decisions in a correctly construction fashion. Creating design restrictions that minimize or eliminate certain noise sources or noise-sensitive blocks or nets prior to implementation will greatly enhance SI closure productivity.

Task 113. Fill in the gaps with the correct variant:

1. In order to efficiently achieve SI closure certain design methodology decisions should be made up...

a) back b) front c) side

2. SI avoidance is the most efficient way to achieve SI closure, but it needs to be balanced against trade-offs of the design metrics such as ….., ….. and ….. .

a) area, performance, and power

b) square, work, and energy

c) surface, operation and force

3. However, if this approach is applied everywhere in the design the result is a much larger die and ….. cost.

a) reduced b) increased c) decreased

4. For certain critical nets, such as clocks or chip-level buses, a practical solution could involve using wider wires, shielding with power and ground lines, using repeaters to break up wire lengths, using different routing layers for adjacent wires, or using ….. spacing.

a) 2-3x minimum b) 3-4x maximum c) 5-6x minimum

5. Other up-front decisions can be based around the selection of …..

a) noise-sensitive blocks

b) noise sources

c) intelligent property (IP) blocks

Task 114. Match up the words with the definition.

p erformance	approximation; act of approaching
requirement	order
implementation	carrying out; doing, execution (of command)
approach	the use of; using, something, application

Task 115. Look through the text again and find the following words in the sentences:

1. design methodology decisions

2. market requirements

3. coupling capacitance

4. grounded capacitance

5. practical solution

6. IP blocks

7. I/Os

8. digital or analog cores

Task 116. Organizing your thoughts:

1. Why should be done in order to efficiently achieve SI closure?

2. What is the most efficient way to achieve SI closure?

3. In what way can most SI problems be avoided?

4. What is a practical solution for certain critical nets?

5. What can other up-front decisions be based on?

Task 117. Sum up the text using the following plan:

1. Efficient ways to achieve SI closure.

2. Solution of most SI problems.

3. Other up-front decisions.

Task 118. Skim the following text and try to understand the subject-matter

of the text.

TEXT 1C:

SI PREVENTION

A number of techniques can be used to prevent SI problems during design creation. During placement for example, the placement can be optimized to avoid over-congested areas. Congested areas increase the likelihood of congested wires leading to an increase in crosstalk. Other techniques during placement include balancing slews within the design so that there are no very fast or very slow signal transitions. Very fast transitions when present on aggressors will lead to an increase in crosstalk. Weakly driven nets with slow transitions are potential crosstalk victims if there is significant coupling on these nets. Typical examples of weakly driven nets are non-timing critical signals such as resets or scan lines. These nets tend to be long and, consequently, subject to many potential aggressors. A noise glitch on a reset line can cause intermittent resetting of a chip while a noise failure on the scan line will make testing a design very problematic. Using these heuristics during placement greatly decreases the occurrence of these types of SI failures.

While SI prevention during placement will help reduce certain SI problems, the main prevention effort should come during routing. As SI is inherently a wiring problem, it has become necessary to address SI prevention as the design is being routed. Crosstalk effects, such as glitch and delay, can only effectively be measured when physical wires are available and final wire topology, layer selection, and track assignments are concrete. Since placement-based and global route-based SI prevention solutions do not have this detailed information with which to make trade-offs, they are only a partial solution. In the nanometer era, physical wire effects need to be taken into account to achieve reliable timing and SI closure during the final routing stage of the design (see Figure 21).

Figure 21: Slew balancing to reduce crosstalk glitch and delay effects

The key to successful SI closure during routing comes from having native on-the-fly incremental extraction, timing analysis, SI analysis, and optimization. This means that potential SI problems can be addressed as they occur. A number of prevention techniques can be employed during routing to correct SI issues:

• Wire spacing

• Net ordering

• Layer selection to reduce coupling and resistance

• Minimizing parallel wire lengths

• Shielding

• Buffer insertion

• Gate resizing (see Figure 22).

Figure 22: SI avoidance techniques during routing

Many of the above techniques require the detailed router to use a graph-based approach that supports variable width and variable spacing so that SI issues can be addressed effectively without impacting overall area. While SI analysis during routing should be accurate enough to guide the process, it must also be fast and not overburden the routing process itself. The router should also permit trade-offs in terms of meeting performance and area goals as well as preventing SI problems.

Task 119. Find sentences with the following words.

1. crosstalk – перекрестные помехи

2. noise glitch – шумовой всплеск

3. heuristics – эвристика

4. delay – задержка

5. graph-based approach – подход основанный на графиках, диаграммах

Task 120. Comprehension check:

1. What techniques can be used to prevent SI problems during design creation?

2. Which are typical examples of weakly driven nets?

3. What can a noise glitch on a reset line cause?

4. What is the key to successful SI closure during routing?

5. Enumerate a number of prevention techniques which can be employed during routing to correct SI issues.

Task 121. Match up the words with the definition.

t echnique	resolution into simple elements
analysis	Resolution, solving, answer, method for solving a problem
solution	aims, purposes
goals	Mode of execution, of performance or work

ACTIVITY 2

Task 122. Skim the following text and try to understand the subject-matter of it.

TEXT 2A:

ANALYSIS AND REPAIR

After SI-aware routing is complete, a full detailed extraction and analysis should be performed to determine if there are any remaining SI problems. This analysis should include identifying potential functional and timing problems introduced by SI. Functionality checking should involve calculating the worst-case potential crosstalk glitch that can occur on every wire and propagating that glitch to a storage element such as a latch or flip-flop to determine if it will cause a stored logic state to change.

A noise failure criterion based on latching glitches, rather than noise peak on each victim or noise rejection curves on each receiving cell, will reduce the number of potential repairs by several orders of magnitude. In a SI prevention-based flow that uses noise propagation as the failure criteria, the number of potential violations found post-route should be relatively small, typically fewer than 50 for a design with 500K instances (~2 M gates) at 250 Mhz using a 130 nm process. Consequently, repairing the remaining functional noise problems (if any) is easily achieved through automatic or even manual repair. In contrast, if the noise failure criterion is such that thousands of functional noise problems are reported, then the repair effort can be significant and may not converge.

Figure 23: SI repair techniques

To repair glitch problems, a number of techniques can be used such as 1) upsizing to strengthen the victim’s driver, 2) down-sizing aggressors’ drivers, 3) buffer or repeater insertion to break down crosstalk effects into smaller constituents, 4) and spacing, shielding or re-routing wires. The key to successful convergence on repair is to find the best solution that creates the least disturbance to the existing design. For example, if re-routing a net to reduce coupling, the original timing can be maintained by restricting the length of the new route to be similar to the original route (see Figure 23).

More challenging than fixing functional violations, however, is fixing the impact SI has on timing. The additional delay changes caused by crosstalk increase the degree of difficulty for achieving timing closure. First a post-route static timing analysis of the design must be performed to determine if any new setup or hold violations have been introduced by SI. Each new failing path needs to be re-optimized. This timing repair process must endeavor to fix the failing paths with the minimum of design disturbance while identifying the optimal way to regain lost time. Fixes for timing violations can include traditional in-place optimizations as well as crosstalk reduction techniques such as those used to repair functional violations. To converge quickly on repairs, both functional and timing problems should be repaired simultaneously. As each potential repair is implemented it should be incrementally analyzed to determine if it really fixes the problem and to ensure it does not introduce a new timing or functional glitch.

After all repairs have been implemented, the design should be considered closed and ready for final verification and SI sign-off.

Task 123. Comprehension check:

1. What should be done after SI-aware routing is complete?

2. What should this analysis include?

3. What techniques can be used to repair glitch problems?

4. What is the key to successful convergence on repair?

Task 124. Fill in the gaps with the correct variant:

1. The analysis should include identifying potential ….. and timing problems introduced by SI.

a) functional b) external c) internal

2. The key to successful ….. on repair is to find the best solution that creates the least disturbance to the existing design.

a) convergence b) transition c) transplantation

3. The additional delay changes caused by crosstalk ….. the degree of difficulty for achieving timing closure.

a) decrease b) reduce c) increase

4. Each new failing path needs to be …..

a) re-elected b) re-optimized c) re-organized

5. After all repairs have been implemented, the design should be considered closed and ready for final ….. and SI sign-off.

a) verification b) calculation c) implementation

Task 125. Sum up the text using the following plan.

1. Actions to be performed, after SI-aware routing is complete.

2. Repairing the functional noise problems.

3. Techniques used to repair glitch problems.

Task 126. Skim the following passage trying to understand it and give a title to it:

TEXT 2B:

For nanometer designs timing closure is not sufficient to guarantee a working chip because it only ensures a design will operate at the desired clock frequency if it is noise free. In nanometer processes SI effects are inherent due to the high percentage of coupling capacitance versus total capacitance. Consequently, true timing closure can only be achieved when SI is taken into account. Furthermore, SI can cause functional problems. To achieve SI closure both functional and SI effects on timing must be addressed and corrected before sign-off.

Addressing SI problems after achieving timing closure is also no longer effective. The number of potential SI problems has increased substantially in the nanometer era such that SI must be tackled as the design is implemented, particularly during detailed routing. The implementation flow should strive to create an SI-clean design while still meeting other design metrics such as performance, area, and power. The flow needs to be flexible to permit trade-offs in terms of turnaround time versus creating an optimal design. Finally, the flow should support post-route repair to find and quickly fix any remaining SI-induced violations without causing any new design iterations.

An integrated SI closure approach involving prevention, analysis, and correction will significantly reduce the design cycle and, as a result, the time to market. The adoption of such an SI closure methodology will be a key determinant of success for nanometer designs.

Task 127. Comprehension check.

1. Why is timing closure for nanometer designs not sufficient to guarantee a working chip?

2. In what way can true timing closure be achieved?

3. What must be done to achieve SI closure?

4. What will be a key determinant of success for nanometer designs?

Task 128. Skim the following text trying to understand the subject-matter of it.

TEXT 2C:

NANOMETER TECHNOLOGY TRENDS

Timing sign-off is where the digital design process comes to a crunch. The goal of timing analysis is to ensure that a design will operate at the required clock frequency when it is fabricated. If the chip fails to meet its performance target, designers must implement engineering change orders–ECOs–to fix reported timing problems. Designers repeat this process until the design reaches timing closure. If designers are lucky, they reach this point within just a few iterations. But as they adopt nanometer technologies (0.18μm and below), designers find that measured silicon performance varies considerably from timing tool predictions, so additional iterations are necessary at the point where they are most costly–after fabrication.

Static timing analysis is generally the accepted timing verification method of choice for digital designers. However, most static timing tools ignore one of the key electrical side effects of nanometer processes–crosstalk induced by the simultaneous switching of neighboring wires. Crosstalk effects can distort waveforms and alter their time of flight, and so play havoc with the integrity of switching signals. If designers ignore or overestimate the impact of crosstalk on delay, designs either under perform or go through unnecessary design iterations to fix problems that don’t really exist in silicon. Either way, the net effect is a product that is late to market.

Advances in nanometer process technology aggravate timing problems because each new generation brings shrinking feature sizes, wire width, and wire spacing. The reduction in wire width means a decrease in total wire capacitance.

But it also means a dramatic increase in the fraction of wire capacitance resulting from lateral coupling. In this age of system-on-a-chip (SoC) design, die sizes have remained relatively constant as more and more functionality is crammed onto a single chip. Consequently, average wire length has remained relatively constant despite decreasing wire pitch.

The continued demand for improved performance compounds the crosstalk problem. Improved performance translates to higher clock frequencies, with much faster switching signals. As signals switch faster and faster, more noise couples onto neighboring lines. Measuring the impact of crosstalk is therefore a critical step in determining whether a design will function as expected at the required performance target.

Task 129. Comprehension check:

1. What is the goal of timing analysis?

2. What can crosstalk effects cause?

3. Why do advances in nanometer process technology aggravate timing problems?

4. What does the reduction of wire width mean?

Task 130. Skim the passage and sum up crosstalk decreasing signal delay.

TEXT 2D:

CROSSTALK IN DIGITAL DESIGNS

Figure 24: Victim net with two coupling aggressors

Figure 25: Crosstalk increasing signal delay

Figure 25 shows an example of the effect of crosstalk on delay for the circuit given in figure 24. The yellow waveform shows the victim signal at the receiving gate when there is no crosstalk. The green waveform shows the victim when it is attacked by an aggressor signal switching in the opposite direction. In this example the additional crosstalkinduced delay is greater than the delay of the gate without crosstalk. If the affected signal forms part of a critical maximum delay path, the extra delay due to crosstalk can cause the signal to arrive too late at a latch or a flip-flop, resulting in a setup failure.

Figure 26: Crosstalk decreasing signal delay

Crosstalk can also decrease delay, as shown in figure 26. In this case, the aggressor signals (blue) switch in the same direction as the victim signal (light blue). If this occurs on a critical minimum delay path it can lead to hold violations–data arrives too early at a latch or a flip-flop. Setup failures are undesirable, but they can be removed by slowing the clock and accepting lower performance. Hold violations, however, can be fixed only by making costly silicon mask changes.

Crosstalk-induced delay effects are not limited to the nets where the attack occurs. Figure 2 shows the typical waveform shape, complete with the camel’s hump that results when an aggressor signal attacks while a victim signal transitions.

This non-monotonic waveform also impacts the delay of the following logic gate. Consequently, crosstalk effects can percolate through a circuit, and dramatically alter its timing characteristics.

Task 131. Find the sentences with the following words:

crosstalk – перекрестные помехи, перекрестные искажения

flip-flop – триггер, триггерная схема; бистабильная ячейка

latch – триггер-фиксатор; регистр-защелка

logic gate – логический элемент

Task 132. Which of the following do you think is true or false?

1. If the affected signal forms part of a critical maximum delay path, the extra delay due to crosstalk can cause the signal to arrive too early at a latch or a flip-flop, resulting in a setup failure.

2. Crosstalk can also decrease delay.

3. Setup failures are desirable, but they can be removed by slowing the clock and accepting lower performance.

4. Hold violations, however, can be fixed only by making costly germanium mask changes.

5. Crosstalk – induced delay effects are not limited to the nets where the attack occurs.

Task 133. Study the following words and word combinations:

IC – integrated circuit – интегральная схема

Power grid – электроэнергетическая система; электрическая сеть

I/O pins – контакты входа-выхода

IR drop – активное (омическое) падение напряжения; падение

напряжения на внутреннем активном сопротивлении

RC elements – элементы радиоуправления; элементы

дистанционного управления

Task 134. Skim the text and try to get its main idea.

TEXT 2 E:

POWER GRID IR DROP AND GROUND BOUNCE

C power distribution systems are designed to provide needed voltages and currents to the transistors that perform the logic functions of a chip. Based on a survey of over 206 tapeouts, targeting process technology of 0.13 micron or greater, more than 50% of tapeouts will fail if the power distribution system is not validated beforehand. At and below 0.13 micron technologies, IC designers can no longer take the risk of assuming that their VDD and VSS grids have been designed correctly, and they must perform detailed analysis to understand how robust their power distribution methodology really is.

The performance of a design’s power networks, or grid, has a direct impact on its performance. Voltage (IR) drops on VDD nets and ground bounce on VSS nets affect a design's overall timing and functionality, and if ignored, will cause silicon failure. High currents in the power grids also induce electromigration (EM) effects, where the metal lines of a power grid begin to wear out during a chip’s lifetime. These effects cause expensive field failures and major product liability issues.

While a clean power grid design should always be the goal of any design team, timing analysis should be performed with the effects of IR drop and ground bounce included once the power grid is routed – it is always possible that a designer can simply live with the amount of IR drop if it does not cause timing failure.

A complete picture of power grid robustness can only be obtained when effects such as IR drop, ground bounce, and EM are accurately computed and analyzed. These are full-chip issues that must be addressed by verification tools that have the capacity and performance required to analyze detailed representations of the chip in a reasonable amount of time. By analyzing and verifying the power grids at the full-chip level, designs can be taped-out with an increased expectation of first silicon success. In this white paper, the key issues of power grid design–IR drop, ground bounce, and EM – are described, along with the related analysis issues. Methodologies used to identify IR drop violations and potential EM violations in the power grids are also described, along with approaches that reduce the severity of these problems. Designing with these issues in mind and performing full-chip power grid verification enables designers to address what would otherwise be an intractable problem.

IR drop on a VDD grid is caused because the current demanded by the transistors or gates of a design flows from the VDD I/O pins (or bump bonds in the case of flip-chips) through the RC network of the power grid, and leads to a decreased VDD voltage at the devices. Ground bounce is a similar phenomenon, where the current flows back to the VSS pins, and the RC network causes the VSS voltage at the devices to rise. The risk of a design suffering from IR drop or ground bounce increases with shrinking process technology and with next-generation designs.

With every technology shrink, the current demand per unit area of a design is increased, basically because of shrinks in the gate oxide thickness. This, combined with the fact that next-generation designs contain more transistors or gates, adds additional stress to power grid design and typically results in a power grid that contains an increasing number of parasitic RC values to be analyzed. For example, a leading-edge 90nm design containing over 10 million gates and processed with eight layers of metal could produce a VDD grid approaching 1 billion RC elements.

There are two approaches typically used for power grid analysis, static and dynamic. A static analysis solves Ohm's and Kirchoff's laws for a given power network but ignores localized switching effects on the power grid. A dynamic approach performs comprehensive dynamic circuit simulation of the power grid network, which includes localized switching effects. Both approaches have unique value and challenges.

Task 135. Speak about the two approaches typically used for power grid analysis.

Task 136. Read the following text and try to understand the subject-matter of it.

TEXT 2F:

REDUCING IR DROP

Another approach to minimizing IR drop, depicted in Figure 3, is to have a solid grid of Metal 4 and Metal 5 and use a via array to connect the two layers, effectively tying the whole grid to VDD. While this solves the problem at higher levels, it simply shifts the problem down to the lower levels of metal. What about Metal 3 and Metal 2?

Are they wide enough to handle the current levels they will sustain in terms of IR drop and EM?

Figure 27: Vias in a mesh array methodology

Depending on the methodology, lower levels are often left floating until final assembly. Low resistance, high current paths can often be created by random placement of lower blocks. In fact, when you design the logic circuitry in the block, it is not clear where Metal 3 will tap to Metal 4, so you cannot predict the current flow. And if you cannot predict it, you must analyze it.

Part of the grid may have to be removed to route some signals, as shown in Figure 27. Which straps can be removed without introducing problems? If you arbitrarily pick one that is conducting a large amount of current, the excess current must flow in adjacent straps which may push the current density in them beyond acceptable levels. Clearly, such decisions cannot be made without determining the current levels in the straps and then picking ones that have lower current levels. The complexity of the problem requires a set of power grid analysis tools. These examples illustrate that design decisions must be made with a global perspective in mind.

IR drop is a dynamic phenomenon due primarily to simultaneous switching events in a chip such as clocks, bus drivers, and memory decoder drivers. As large drivers begin to switch, the simultaneous demand for current from the power grid stresses the grid. In a static context, IR drops are highest near the center of a design and lowest near VDD connections to the power supply. However, during dynamic operation, these simultaneous switching events can cause severe IR drops anywhere on the chip, and these are the ones that must be identified. These events, usually well known, can be triggered with typically fewer than 100 vectors.

The effect of IR drop on chip performance is significant. IR drop compromises the voltage noise margins of logic

gates, due not only to IR drops in the power grid during the rising edge of a signal, but also to the increase in voltage in the ground grid because of the same phenomenon during the falling edge. Once the noise margins drop below the budgeted amount, typically 10%, the design is not guaranteed to operate properly.

As described earlier, IR drops in the power grid can be caused by two different type of phenomena – IR and Ldi/dt.

Reducing the impact of IR drop in a power distribution system can be accomplished in several ways:

WIDEN THE POWER ROUTES

The simplest approach is to widen the lines that experience the largest voltage drops since increasing the width decreases the resistance (hence the IR drop). However, this may not always be possible due to constraints in the routing area. Via arrays should also be maximized wherever possible, since the resistance associated with a single via can have a significant impact on IR drop.

MAXIMIZE THE USE OF DECOUPLING CAPACITANCE

One effective approach is to use decoupling capacitors between power and ground, which can deliver the additional current needed by the power distribution system. These decoupling caps are usually scattered throughout the power grid, in any available space, and enable the use of the static approach to power grid analysis. Ldi/dt effects can be mitigated by placing large capacitances near the pins.

STAGGER THE SWITCHING

Since IR drop is due primarily to simultaneous switching events, another (more difficult) approach is to stagger the gates that are switching together such that they switch at slightly different times – at least enough to keep the problem within the noise budget. Alternatively, you could reduce the buffer size, but this may not be possible if the design fails to meet performance requirements with smaller devices. Device switching can be staggered to reduce the peak demands of current by introducing delays on the signals driving the gates.

MAXIMIZE THE POWER I/O PINS

A more aggressive solution is to use a ball-grid array, sometimes called solder bumps or C4 bumps, where the power supply connections can be at various points within the chip. This expensive solution requires placing many C4 bumps across the chip to minimize the worst-case IR drop in any location. This solution tends to push EM problems to lower levels of metal that are usually narrower. Also, this solution cannot be used in sensitive areas such as memories and dynamic logic because C4 bumps generate alpha particles that may cause logic value upsets in the sensitive nodes.

Nevertheless, when used appropriately, C4 bumps can reduce IR drop. The key to design is proper placement of the C4 connections, which can only be done effectively with full-chip analysis

Task 137. Give a short summary of the text with the help of fig.27:

ACTIVITY 3