Vocabulary work and situations.
Task 67. Guess the meaning of the following words and word combinations:
joule heating
RMS current density
reliability budgeting
root tools
temperature gradient
Task 68. Try to recognize the words in the following sentences and translate them into Russian.
To manage EM, designers first need to understand …… .
A mean time to failure (MTTF) ….. .
Power grid EM issues can be solved with ….. .
Which electrons flow through wires on a chip, they collide …. .
EM is a thermally activated phenomenon ….. .
Electromigration is due to take momentum exchange between conducting electrons ….. .
Task 69. Define the meaning of such words using English-English dictionary. The first example in given to you.
Electromigration –
to manage –
grid –
Task 70. Match up the words with the definition.
p |
any outburst of violent weather |
to dissipate |
energy, stress |
real |
existing in reality, in fact |
storm |
to go away or cause to away |
ower
SITUATIONS:
Discuss tools which IC designers need for EM.
Comment upon the role of routing.
Figure out the problem of Joule heating and explain the current density.
OUTCLASS ACTIVITY
Task 71. Read the text and pay attention to the electromigration behavior force.
GROWTH – DOMINATED FAILURE
If there is a redundant shunt layer, the initial rapid growth of the void will not produce an open circuit. The shunt layer, usually of a refractory material such as W or TiN, can conduct electricity even if a void exists in the primary Al conductor. These metals can withstand extremely high current densities at high temperatures for very long times.
If failure is defined as an open circuit, they don’t fail. However, for most realistic situations, an open circuit is not a realistic definition of failure. Since a resistance change of about 10 % in global wiring can produce timing errors, the 10 % increase has often been chosen as a failure criterion.
Using a percentage increase as a failure criterion during a test has some problems. The actual damage that causes a failure will be a function of the precise geometry of the test structure and the initial resistance. This is unsatisfying for evaluating real circuits that don’t look like test structures. It is recommended, therefore, that failure criteria be based on an absolute change in resistance, the maximum that a particular circuit can withstand before problems arise.
It is necessary to use test structures that can measure a resistance change without geometric effects, such as the Blech Length to affect the data. In the 1970s Ilan Blech of the Technion in Israel performed one of the most important series of experiments in the history of electromigration science and technology. In these experiments he had created a test structure that consisted of islands of gold (Au) deposited onto a refractory underlay. When current was passed through these samples, the upstream side of the islands moved in the direction of electron flow and the downstream edge stayed stationary. If the island was long enough, extrusions formed on the downstream edge, but if the island was short enough, electromigration essentially stopped. Electromigration also stopped when the longer islands shrunk to a critical level. He discovered that there is a critical product of the current density and the length of the island, below which electromigration ceases. This is the origin of the “Blech Length.” For any given current density, there is a length below which electromigration will not occur.
This behavior occurred because a mechanical back stress, generated by electromigration, resisted the electromigration force. The back stress exists only in the presence of a flux divergence and it is greater in the presence of a mechanically strong confining passivation layer. For this reason, the Blech Length cannot be easily pre-determined. It is a strong function of the process and the physical design of the chip.
In principle, one could make a circuit immortal by designing all the lines to be shorter than a Blech Length. However, the Blech Product jxl is only on the order of a few thousand and is a strong function of the thermal history, so this idea has not been seriously considered.
The growth of a void depends on the rate that metal atoms leave the void, or, equivalently, the rate at which vacancies enter it. The flux of vacancies or atoms is linearly dependent on the current density, and therefore the time required to attain a certain void size will obey 1/j kinetics. Care must be taken in experimental measurements, however, since inappropriate test structures can result in just about any value for the current exponent.
For a given metallization, growth dominated failure must take longer than nucleation dominated failure, since the damage needs to nucleate before it can grow. However, the nucleation phase can be very short, approaching zero.
The kinetics of failure must be evaluated experimentally and applied properly. This means that for electromigration damage in real conductors, we can have either 1/j or 1/j2 kinetics. It has been observed that for wide lines, defined as those where the average grain size is smaller than the line width, 1/j2 kinetics usually dominates, whereas for narrow lines, 1/j kinetics dominate.
Task 72. Read the text and explain the problem of joule heating and its temperature gradients.
JOULE HEATING AND ITS TEMPERATURE GRADIENTS
When current is passed through a conductor, the interaction of the electrons with the lattice produces a thermal energy equal to the product of the square of the current and the resistance. This is called Joule heating. Metal lines will heat up whenever current is passed through them. If the current is low, the heat is effectively conducted away, but there must be some temperature increase even if it is not detectable. If the current density approaches 106 A/cm2, Joule heating can produce enough energy to make the conductor lines heat up appreciably. At first this does not appear to be a problem, since current densities are almost always lower than this due to limitations induced by electromigration. However, one must realize that Joule heating is caused by root mean square (RMS) current and not by the average current, as is electromigration. For a narrow pulse, the RMS current can be much higher than the average current. The average current can be well within any guidelines that may be set for electromigration considerations, yet significant Joule heating can result. This can be more prevalent on upper level metallization, where heat must be conducted through several layers of interlevel dielectric, which is a poor thermal conductor.
The problem with Joule heating is not the modest temperature increase, but the temperature gradients that result. Typically, at the current densities found in modern circuitry, temperature increases would range between a few and a few tens of degrees Celsius. This produces temperature profiles that decay within a few microns, so that temperature gradients of 104 to 105 degrees Celsius/cm will be found. Since electromigration is thermally activated, the temperature gradients produce flux divergences that approach that found at absolute divergences such as at contacts or at microstructural features.
RMS current density must then be limited to about 2 x106 A/cm2 for lower level lines and about half that for upper level lines. Unfortunately, the reliability of metal lines in the presence of temperature gradients cannot be accurately estimated.
Temperature gradients can vary tremendously throughout a real structure, depending on subtleties of the geometry and on the use of the underlying silicon devices. The only way to deal with these issues is to take a conservative approach and forbid temperature gradients by limiting the RMS current density to the levels suggested above.
Task 73. Read the text and skim it up.
MICROSTRUCTURE AND ELECTROMIGRATION LINE WIDTH EFFECT
Electromigration is a form of mass diffusion, where the driving force is provided by the electron flow. Therefore, things that affect diffusion will affect electromigration. Metals are composed of atomic crystals where atoms are lined up very nearly perfectly in only a few allowable configurations. The size of these crystals (“grains”) is finite.
Where the grains meet, they form a region of disorder (“grain boundary”), and provide a pathway for easy diffusion as compared to the nearly perfect metal lattices.
In the early days of ICs, the thin film conductors used in manufacturing were relatively wide, fine grained, and composed of many grains. These were referred to as polycrystalline. The grain size was about the thickness of the film, generally about one micron. Across the width of a typical conductor several microns wide, many grain boundary pathways were available to accommodate the electromigrating atoms. It came as no surprise that electromigration failure was inversely proportional to the grain size of the films: the more grain boundaries present, the more atoms that can be transported along them, and the earlier the failure time.
As line widths became smaller, the grain size of the metal films became larger. Conductor lines became comparable in width to the grain size and took on a “bamboo” like appearance where most of the grains spanned the line width, providing no continuous grain boundary pathway in the direction of the current flow. When this occurred, a peculiar effect was found: failure times were strongly dependent on line width. Narrow lines at the same current density became substantially more reliable than wider lines, as long as the grain size was uniform.
The reason for this behavior was not hard to figure out. The lack of easy grain boundary pathways meant that the atoms had to take more arduous paths such as the lattice or various interfaces in their journeys. The activation energy for failure was found to be a function of line width, since the diffusion process changed. What became even more interesting and important to reliability engineers was that the precise arrangement and orientation of the grains had a large effect on the lifetime of the conductor. In fact, as the ratio of grain size to line width increased, the reliability became poorer before it got better, and then got worse again as lines entered submicron widths.
Today, we understand this behavior and can predict the reliability from test data, grain structure, and particulars of the metal deposition process. New effects, due to the presence of refractory shunt layers and W plugs, have surfaced and have also been explained well enough that they can be tamed. However, a fundamental understanding of the process of solid state diffusion and what affects it are essential in interpreting test results. For this reason, conservative default values for parameters used in relating electromigration test data to real circuits should be employed until careful testing and data interpretation justify a change.
The choice of test structures and test conditions are of critical importance in extracting meaningful parameters to be used in interpreting the test data as it relates to actual chip performance. The wrong test or the wrong test structure can produce fatal results. The test structure must be designed to reflect the process and usually a single structure cannot.
SUPPLEMENTARIES
DESIGN ISSUES THAT CAUSE EM
In the past, wide metal lines and low current densities, combined with special processing, helped minimize the effects of EM. But today’s technology – wires less than 130 nanometers wide, operating frequencies continuously increasing beyond 100 MHz, and no proportional decrease in power dissipation – has increased the potential for EM problems.The only solution is to use design tools and methodologies that minimize the potential for EM and find the problems when they occur.
Design issues related to EM can be divided into two categories: power grid and signal line. In a hierarchical design methodology, designers construct blocks with little or no knowledge of the full-chip environment in which the block will be placed. This creates two problems. (1) The designer responsible for the global power distribution has little information about the implementation of the local power grids within the individual blocks, making it impossible to predict at the top level how power will be routed throughout the chip. (2) Block designers have no knowledge of surrounding blocks, so they don’t know the quality of the power provided to their block or whether their block also serves as power routing to an adjacent block. This information isn’t available until designers assemble all blocks and perform full-chip power analysis.
A common EM design problem occurs when an embedded logic block is placed near the periphery of a chip. In one case, a power bus was routed around a logic block to transmit power into the center of a chip. Unknown to the chip designer, the power wires within the logic block were oriented such that the effective width of the power wires inside the block was greater than the width of the power bus around the block. This resulted in power being inadvertently routed through the block rather than around the block, generating many EM violations inside the logic block (see Figure 8).
Figure 8: EM violations in a logic block are flagged in orange and yellow and superimposed on the image of the power grid
Designing signal wires to minimize EM is a new and rapidly increasing challenge as wire width decreases. Although routing tools can adjust wire width to minimize interconnect delay, they don’t adjust wire widths based on EM concerns. In addition, they don’t have enough knowledge of circuit behavior to know which wires may have EM problems. Since most designers don’t have the tools to adequately analyze power or signal EM, they rely on ad-hoc methods to prevent signal EM and often don’t find the problems until after the chip is manufactured. Ad-hoc methods can yield designs that consume much more area than necessary due to routing.
HOW TO FIND EM BEFORE IT’S TOO LATE
To find EM problems you need to extract and analyze full-chip data. Cadence verification tools, such as VoltageStorm™ and ElectronStorm™, extract and analyze power grid and signal EM. Full-chip EM analysis begins with the extraction from layout of parasitics associated with both signal and power networks. To support EM analysis, and give meaningful feedback to designers, extraction must provide wire segment size, layout layer, and layout location. Key to finding all EM problems is to avoid the use of reduced data because you might eliminate information critical to the power grid and signal EM analyses.
EM analysis also requires current flow data to derive wire current densities. Power grid current behaves as a pulsed DC current whereas signal wire current behaves as both pulsed DC and AC currents. The current behavior characteristics are determined by analyzing the transistor netlist in either static or dynamic mode (using test vectors).
Power grid current characteristics must be derived by simulating the circuit with many vectors, or using average circuit behavior in a static analysis.
Finding signal problems requires two analyses—EM and Joule heating. EM analysis requires average current data on signal lines; Joule heating analysis requires RMS current information. Signal analysis is performed net by net,
simulating the charging and discharging for all possible paths to determine the worst case average and RMS current for each wire segment. Once currents are determined, current density is computed and failure models are applied to each wire segment. Figure 9 shows the locations of signal EM in a chip after applying a Joule heating failure model.
Figure 9: ElectronStorm highlights the locations in signal lines that are subject to Joule heating failures if this chip is operated at 200 MHz