Vocabulary work and situations.
Task 30. Guess the meanings of the following word and word combination.
RTL-to-GDS flow
Leakage power
Encounter RTL Compiler
Power management
Routing
Electrical verification
Task 31. Try to recognize the word in the following sentences and translate them into Russian.
A balanced approach is warranted when it comes to power optimization that spends across the entire RTL-to GDS flow.
Dynamic power dissipation occurs when a circuit is operating.
Register Transfer Level (RTL) and micro-architecture offer a great opportunity to influence dynamic power.
Encounter RTL Compiler does a concurrent optimization of timing, area, and power during RTL elaboration.
Task 32. Define the meaning of such word using the English-English dictionary. The first example in given to you.
Consumption – an act of consuming and using.
Solution
Flow
Power
Task 33. Match up the words with the definition.
RTL-to-GDS flow |
управление мощностью |
Leakage power |
трассировка |
E ncounter RTL Compiler |
электрическая проверка |
Power management |
утечка мощности |
Routing |
компилятор резисторно-транзисторных логических схем |
Electrical verification |
процесс проектирования резисторно-транзисторных логических схем с универсальной системой данных |
SITUATIONS:
Use Fig.2 and give explanation about power management.
Discuss the aspects of power awareness.
Comment upon new systems and architecture design.
Share your opinion of the power management of design flow.
OUTCLASS ACTIVITY
Task 34. Read the text and pay attention to the multiple “voltage islands”.
DESIGN WITH MULTIPLE VOLTAGE ISLANDS
Voltage scaling is an obvious technique to gain significant power saving for any low-power design. In an example of reducing the voltage from 1.0V to 0.8V (20% reduction), while assuming both the capacitance (C) and the switching frequency (f) remain the same, one would gain up to 36% dynamic power reduction. This emerging design approach can have a major impact on optimizing power consumption, and promises to become an effective strategy. The technique is based on “islands” of cells, each with different supply voltages (Vdd). The less timing-critical logic can have a scaled-down voltage supply, at a cost of slower timing performance. These voltage islands can even be turned off completely when not in use. When a signal goes through these islands, it needs to pass through level shifters to keep it at appropriate voltages and also clamp cells, in case islands are turned off.
Previously, these operations made designing with multiple voltages impractical for many implementation systems, or required complicated manual processes throughout the implementation flow. The Encounter platform provides complete support and a simplified process for implementing multiple voltage islands in all steps of the design – such as floorplanning, partitioning, placement, optimization, routing, and timing – to make this flow possible.
Task 35. Read the text and explain partition and floorplanning and power consumption.
DESIGN PARTITIONING AND FLOORPLANNING
Design partitioning and floorplanning play an important role in reducing overall power consumption. For example, wires with high switching probabilities must be kept within a partition to reduce capacitance.
Placing blocks in the correct positions can dramatically decrease the total capacitance. Cell placement affects power dissipation because placing cells far from each other increases the wire length, which increases switching capacitance. Until recently, accurate placement required many iterations, because prediction of which wires contribute most of the capacitance has been difficult. A multi-supply voltage design needs special treatment when it comes to partitioning and floorplanning. The ability to specify and understand multiple voltage regions is a key requirement for modern floorplanners. The Cadence Encounter platform satisfies this requirement with an easy-to-use multi-supply voltage partitioning step.
Task 36. Read the text and get information about the effective currents models.
TIMING ANALYSIS AND ECSM
Using multiple power supplies within the chip complicates the timing analysis step because the tools need to pick appropriate cell models for computing the timing. Proper modeling for level-shifter and clamp cells is also needed to compute the delays correctly. Especially in the ultra-deep sub-micron technology of 130 nm and below, accuracy requirements have never been more demanding. The effective current source model (ECSM) helps in this regard. This model relies on the current drawn by elements, as opposed to the voltages that traditional models use. The greater accuracy of this model results from the current being a better linear function than voltage when analyzed for time. Average differences between ECSM and SPICE results were less than 0.5%, with the maximum less than 2%, in tests conducted by two major foundries in 130-nm and 90-nm technologies (see Figure 6).
Figure 6: Modeling accuracy comparison of ECSM and SPICE
ECSM facilitates accurate analysis in many situations in which conventional models fail. For example, multiple supply voltages and multiple driver nets can be easily handled by ECSM. Characterization efforts for libraries tend to be simpler with ECSM. In multi-supply multi-voltage (MSMV) designs, different operating voltages can be covered with just one ECSM library, which is characterized with just three points across the voltage range.
Figure 7: Accuracy across a range of voltages – comparison of ECSM and SPICE
In Figure 7, the same excellent accuracy of within 0.5% of SPICE was maintained from an operating range of 0.6V to 1.32V with one ECSM table. This, compared to the traditional requirement of one characterized library for each operating voltage, can offer the designer a breakthrough freedom in deciding on the most effective MSMV design to meet overall design goals.
Task 37. Read the text and share you ideas on Encounter Platform which provides the automatic power planner (APP).
POWER PLANNING/ROUTING
Power planning/routing is an important step that ensures proper power distribution to the leaf cells. Using the power domain concept to identify different voltage “islands,” the Encounter platform has built-in automation to aid the user in associating the correct power supply with each of the domains, and building the appropriate power structure efficiently. This power domain capability also extends to automation of the insertion and placement of the level-shifter cells, as well as the proper cell placement optimization within the domain, which reduces the major barrier to designing with multiple voltage islands. To further reduce the physical design effort, the Encounter platform also provides the automatic power planner (APP), which allows designers to optimize the power-grid network earlier in the design flow, based on accurate physical data. Users can define various power templates for the macros and the chip, and perform “what if” power analysis to find the optimum template. Once a particular template is chosen, APP can synthesize an optimal power grid based on the power requirements and the IR drop constraints. As the design undergoes further power optimization, users can then trade off the extra power savings against area or timing. This also provides an excellent way to handle IR drop-based timing violations.
SUPLIMENTARIES
LEAKAGE POWER OPTIMIZATION
To manage the growing problem of leakage power dissipation, a proven approach is to use a complementary set of two or more libraries containing matching sets of logic cells. The sets of cells are the same except for the threshold voltages (Vt). Cell libraries with higher Vt operate at lower frequency and dissipate significantly less leakage power than libraries with lower Vt. The aim of this design methodology is to restrict use of lower-Vt cells to critical paths and use high-Vt cells on noncritical paths during both the logic and physical synthesis stages. The typical approach had been to apply multiple-pass synthesis, using one library at a time to either fix timing or reduce power, but not at the same time. There were also published utility scripts for manually swapping cells.
The disadvantage of these approaches is the difficulty in finding the right balance for optimized timing and power. An overly aggressive approach with high-Vt cells could cause a timing closure problem, while very passive use of high-Vt cells would leave the design underoptimized regarding leakage power consumption. Cadence’s low-power synthesis features can perform analysis and optimization of leakage power during the RTL-to-netlist synthesis flow with a single-pass solution. Encounter RTL Compiler can accurately analyze multiple-Vt cell libraries simultaneously, and can support static, dynamic, and statedependent leakage power models. (Cell power models are also supported for accurate cell power analysis.) Leakage power optimization can reduce leakage power dissipation 30% to 70%, while enabling replacement of 50% to 95% of the cells with high-Vt cells.
In an effective power management flow, the majority of the low-leakage optimization is done at the synthesis level. However, users can benefit from the leakage power optimization capability during the physical implementation phase. This optimization, running at the post- route level with more accurate routed parasitic information, can fine-tune the leakage power consumption while enabling the design to meet timing requirements. The Encounter platform offers effective leakage optimization using multiple-Vt libraries at the gate level, and operates concurrently with other types of optimization techniques to meet the design goal.
SILICON VIRTUAL PROTOTYPING
Today, new silicon virtual prototyping (SVP) capabilities enable designers to have a quick preview of the silicon performance of their design. Because, in today’s technologies, wire capacitance dominates the transistor caps, designers need to assess the route performance quickly to get the actual power numbers.
SVP also helps to reduce local congestion or hot spots, and thus increases power efficiency. Designers can also use selective voltage scaling (multiple supply voltage islands) to reduce power on certain blocks – a major advantage when designing systems-on-a-chip (SoCs) from various off-the-shelf IP elements. Design implementation must consider chip temperature (thermal distribution), because it can contribute to leakage power surges. SVP helps designers analyze and correct potential hot spots. The Cadence Encounter platform supports silicon virtual prototyping for designs using multiple supply voltages.
NANOROUTE ROUTING
The Cadence NanoRoute™ multi-supply voltage and multi-Vt aware router has automatic signal electromigration (EM) prevention and fixing capabilities. Signal electromigration (AC electromigration, also called wire self-heat) is a physical breakage of metal in the field caused by constant contraction and expansion due to thermal stress. Because the current densities are very high in nanometer design processes, the probability of signal EM has increased considerably. This phenomenon is difficult to detect because the failure happens in the field. The Encounter platform can accurately compute the AC current density on signals and check against the foundry-provided limits. Wide wires and buffer insertion are used to fix the errors.
DESIGN INTEGRITY AND ANALYSIS
While different techniques can be used to aggressively manage both dynamic power and leakage power, the effect of lowering operating voltage and low leakage cells also presents challenges to design integrity. Lower voltage would be more sensitive to signal integrity (SI) issues; EM and IR drop would have larger effects; and performing accurate timing analysis across different voltage ranges and domains is a potentially complicated manual process.
SWITCHING AND SHORT-CIRCUIT POWER MANAGEMENT
Design implementation to minimize switching power can result in local areas where there is a lot of switching activity (for example, around the sense amplifier regions in RAMs). These areas can dissipate more power when all components switch simultaneously, and can result in significant dynamic IR drop. To counter this effect, designers can place a number of decoupling capacitors around the area to act as charge stores. These cells supply the additional power needed during simultaneous switching.
However, adding decoupling capacitors increases the overall leakage power dissipation, and the placement also impacts the actual effectiveness of the solution; therefore, this technique must be used carefully. VoltageStorm® power-grid verification offers an effective capability to analyze and recommend the insertion and placement of optimized decoupling capacitance to enable the intelligent use of this technique for reducing switching power.
Short-circuit power dissipation is controlled by regulating the transition times of the signals. Typically, designers place a limit on the transition time (10% of the clock cycle, for example), and then optimize the design to meet this limit. Beyond this point, short-circuit power dissipation cannot be controlled. Shortcircuit current is also a function of drive strength, so the capacitive loading would have a direct impact as well. Optimizing the short-circuit power dissipation would be covered by the integrated timing and optimization capability of the Encounter platform.
SIGN-OFF POWER ANALYSIS
Accuracy has been the primary criterion in selecting a sign-off tool. In nanometer processes, this has a new meaning. Because of the difficulty in optimizing across multiple objective functions (timing, area, power, and signal integrity), designers are left little margin with which to play. The accuracy of the tool can therefore determine not only how many iterations are needed, but also whether the design will meet all of its goals.
VoltageStorm power-grid verification plays an important role in achieving the level of accuracy of power analysis that the modern processes demand. VoltageStorm, in collaboration with CeltIC™ NDC signal integrity analysis and repair, includes sign-off power analysis for gates and transistors. Timing verification supports the use of multiple voltages, with tools for timing analysis, sign-off level delay calculation, and noise analysis to detect crosstalk. The power integrity analysis of VoltageStorm also enables understanding of IR and EM effects for multiple voltages as well as delay calculations that take IR drop into account. VoltageStorm also provides dynamic power analysis in a vectorless mode.
CONCLUSION
The Cadence low-power design flow is more than a collection of tools that specifically address power as a design issue – critical though that is. This design flow offers not only the most advanced and effective technology, but also the usability and automation to address the overall design goal of best QoS, as well as reduce barriers to design excellence. This practical approach adds power as a new objective function (along with area and timing) during all stages of the design. The tools provide ways for designers to gain understanding of the tradeoffs and provide appropriate optimizations to maximize benefits across area, timing, and power.
The Cadence low-power design flow also provides designers the opportunity to influence power when the leverage is the greatest – at the RTL level. Encounter RTL Compiler optimizes both switching and leakage power in one pass. A multi-supply voltage region based flow is completely supported through the implementation, with multiple supply voltages supported at all stages such as placement, static timing analysis, and optimization. The flow does not end there. The accurate analysis through VoltageStorm and CeltIC NDC, as well as the use of ECSM, gives the user confidence about performance and the design schedule. The Cadence low-power design flow truly makes an impact in nanometer IC designs.
A POWER GLOSSARY
Three basic components contribute to the average power dissipation (Pavg) in an integrated circuit. This section provides useful equations and defines the terminology of power. Pavg can be expressed in the following equation:
Pavg = Pshort + Pleakage + Pdynamic
where:
Pshort – is the power from stacked positive and negative devices in a CMOS logic gate, both being in the “on” state simultaneously. This happens briefly during switching. Pshort usually accounts for 20 % of the overall power and can be controlled by minimizing the transition times on nets.
Pleakage – is the power dissipation due to spurious current in the nonconducting state of a transistor. As geometries shrink and threshold voltages drop, leakage current has become a larger problem. For example, the leakage current in a chip with a threshold voltage of 0.7V, produced using a 0.13-μm process, is about 10–20 pA per transistor. When the same process is used and the threshold voltage is reduced to 0.2–0.3V, the leakage current skyrockets to 10–20 nA per transistor. For a chip with 10M transistors, leakage power can increase from 0.15 mW to 150 mW due to the lower-threshold voltages.
Pdynamic is the dynamic power dissipation, also called switching power. This is the major source of power dissipation in CMOS SoCs, accounting for about 75% of all power dissipation. Pdynamic can be expressed as the following equation:
Pdynamic = CV2fp
where:
C – is the overall capacitance that is to be charged and discharged. The intense scaling of the technology has resulted in smaller transistors and thus smaller transistor capacitances. However, interconnect capacitance has not scaled with the process, as more systems are packed on a single chip.
This has increased the number of interconnects and thus the overall power dissipated for newergeneration designs, and has made interconnect capacitance the dominant component of capacitance.
V – is the supply voltage of the component. Voltage scaling has the largest impact on power dissipation.
f – is the switching frequency of the component. A clock network itself switches twice every clock cycle, and the average frequencies of designs have increased.
p – is the switching probability of signals. For example, in a microprocessor, signals inside instruction RAMs may switch every two cycles (p = 0.5), while signals inside data RAMs may switch only once in every four cycles (p = 0.25). Switching probabilities tend to increase as the need for bandwidth increases, and as designers resort to time-sharing techniques to minimize area.