Vocabulary work and situations.

Task 138. Guess the meanings of the following words and word combinations:

Phenomena

Distribution

Effective

Solution

Sensitive areas

Alpha particles

Task 139. Try to recognize the words in the following sentences and translate them into Russian.

1. As described earlier, IR drops in the power grid can be caused by two different types of phenomena – IR and Ldi/dt.

2. Reducing the impact of IR drop in a power distribution system can be accomplished in several ways.

3. One effective approach is to use decoupling capacitors between power and ground which can deliver the additional current needed by the power distribution system.

4. A more aggressive solution is to use a ball-grid array, sometimes called solder bumps or C4 bumps, where the power supply connections can be at various points within the chip.

5. Also this solution cannot be used in sensitive areas such as memories and dynamic logic because C4 bumps generate.

Task 140. Define the meaning of each word with the help of an English-English dictionary. The first example is given to you.

System – complex whole, set of connected things, or parts, organized body of material or immaterial things.

Approach –

Resistance –

Solution –

Metal –

Analysis –

Device –

Array –

Task 141. Match up the words with their definitions:

G oal	Method, way of doing or performing something
technique	Invention, thing adapted for a purpose
power	Purpose, aim
device	Vigour, energy

SITUATIONS:

1. Discuss the ways of reducing IR drops.

2. Speak about the approach to minimizing IR drop depicted in Fig.27

3. Discuss the effect of IR drop on chip performance.

OUTCLASS ACTIVITY

Task 142. Read the text and pay attention to the concepts on which most static approaches are based.

STATIC POWER GRID ANALYSIS

The static power grid analysis approach was created to provide comprehensive coverage without the requirement of extensive circuit simulations. Typically, most static approaches are based on similar concepts:

1. The parasitic resistance of the power grid is extracted

2. A resistor matrix of the power grid is built

3. An average current for each transistor or gate connected to the power grid is calculated

4. The average currents are distributed around the resistance matrix, based on the physical location of the transistor

or gate

5. At every VDD I/O pin, a source of VDD is applied to the matrix

6. A static matrix solve is then used to calculate the currents and IR drops throughout the resistance matrix

A static approach approximates the effects of dynamic switching on the power grid by making the assumption that de-coupling capacitances between VDD and VSS smooth out the dynamic peaks of IR drop or ground bounce.

The main value of the static approach is its simplicity and comprehensive coverage. Since only parasitic resistance of the power grid is required the extraction task is minimized, and since every transistor or gate provides an average loading to the power grid the solution provides comprehensive coverage of the power grid.

The main challenge of the static approach is accuracy. Local dynamic effects are not accounted for, neither are package inductance effects (Ldi/dt), both of which may result in optimistic IR drop or ground bounce results if there is insufficient de-coupling capacitance on the power grid.

Task 143. Read the text again and enumerate the concepts.

Task 144. Read the text and get information about reducing electro–migration problems.

DYNAMIC POWER GRID ANALYSIS

A dynamic power grid analysis requires that both resistance and capacitance of the power grid are extracted, and that a dynamic circuit simulation of the resistant RC matrix is completed. Typically, the steps to complete a dynamic power grid analysis are:

1. The parasitic resistance and capacitance of the power grid is extracted

2. The parasitic resistance and capacitance of the signal nets is extracted

3. The design netlist is extracted

4. A circuit netlist is created from the extracted parasitics and netlists

5. A circuit simulation is executed, based on a suite of simulation vectors, which simulates the transistors or gates dynamically switching and the effect of this switching on the power grid. The main value of the dynamic approach is its accuracy. Since the results are based on circuit simulation, the IR drop and ground bounce results can be extremely accurate and take into account localized dynamic and package inductance effects.

The challenges of the dynamic approach are significant.

• The parasitic extraction demands are high because you need to extract resistance and capacitance for the power grids and (as a minimum) the capacitance for the signal nets.

• The circuit simulation can contain a huge number of elements to be simulated, which strains the capacity of the circuit simulation engine.

• The vector set that is used to stimulate the simulation plays a dominant role in determining the quality of the output, if a comprehensive suite of vectors is not used, then the results will be questionable because sections of the power grid may not have been simulated.

• Finally, given the number of elements associated with a single power grid, a power grid analysis solution based on comprehensive dynamic simulation will not easily scale as design sizes continue to grow.

Many power grid analysis solutions that promote a dynamic approach must often resort to RC reduction techniques to manage the size of the data to be simulated; however, this directly conflicts with the main value of the dynamic approach, the accuracy of the results. RC reduction of the power grid can cause inaccuracies to creep into the analysis, and can hide real EM problems.

SUPPLEMENTARIES

The following table shows results from a number of 130 nm customer designs that have been implemented using the Cadence^® SI closure flow that is an integral part of SoC Encounter™. In each case the design has been successfully fabricated without any SI-related problems. In addition, all of the designs operated at the desired clock frequency (see Figure 28).

Figure 28: Results of using SI closure on real 130 nm designs