EISA System Architecture

Translator

Address Translation

The EISA chipset must translate the address being generated by the bus master to forms that are understood by the slave devices on all three buses. Table 11-3 defines the different forms of address information expected by devices on the three buses.

Table 11-3. Address Translation Table

When an EISA bus master or the host CPU is performing a bus cycle, the EISA chipset must convert the bus master's byte enable outputs, BE#[3:0], into the correct setting on the A0, A1 and BHE# signal lines. Conversely, when an ISA bus master is performing a bus cycle, A0, A1 and BHE# must be converted to the correct setting on the byte enable lines.

Command Line Translation

Each of the three types of bus masters, EISA, ISA and host CPU, uses a specific set of signal lines to indicate the address phase and data phase periods and the type of bus cycle in progress. Conversely, each of the three types of slaves recognizes the same respective set of signals indicating address phase, data phase and the bus cycle type. When a bus master initiates a bus cycle, the EISA chipset must convert the bus master's signal set to those recognized by the other

128