EISA System Architecture
Table 8-4. Type A Transfer Rates
|
I/O Device Size |
|
|
Transfer Rate |
|
|
|
|
|
|
|
|
8-bit |
|
|
1.388MB/second |
|
|
16-bit |
|
|
2.777MB/second |
|
|
32-bit |
|
|
5.555MB/second |
|
When a DMA channel is programmed to use the Type A DMA bus cycle to transfer data, the channel may be used to transfer data between fast, EISA memory and an I/O device designed for Type A transfers. In addition, many older, ISA I/O devices may also work with a channel programmed for Type A bus cycles. This is because the Type A transfer does not involve a significant amount of compression compared to the ISA-compatible bus cycle. Compatibility may be determined by testing.
Type B DMA Bus Cycle
Description
When programmed to use Type B DMA bus cycles, a transfer is performed every four BCLK periods. Table 8-5 defines the duration of key signals during a Type B DMA bus cycle.
Table 8-5. The DMA Type B Bus Cycle
|
Event |
|
|
Duration |
|
|
|
|
|
|
|
|
Memory address present |
|
|
4.0 BCLKs |
|
|
Duration of data transfer period during a memory to IO transfer |
|
|
2.5 BCLKs |
|
|
(CMD# active) |
|
|
|
|
|
Duration of IORC# during I/O to memory transfer |
|
|
3.5 BCLKs |
|
|
Duration of IOWC# during a memory to IO transfer |
|
|
2.0 BCLKs |
|
The duration of the key signals illustrated in table 8-5 defines the amount of time the memory and I/O device have to recognize that they are being addressed and to either accept or output data. When performing Type B bus cycles, the DMA controller uses W/R# rather than MRDC# or MWTC# to indicate the type of memory operation,.
86