EISA System Architecture

•Memory Write

•I/O Read

•I/O Write

In an EISA system, the main CPU is capable of performing three variants of each of these four bus cycle types when communicating with a device over the EISA bus:

•Standard timing

•Compressed timing (not implemented in current machines)

•Burst timing

EISA bus masters are capable of executing two of these three variants:

•Standard timing

•Burst timing

Standard EISA Bus Cycle

General

The standard EISA bus cycle type is based upon a zero wait state bus cycle. Unless wait states are inserted by the slave, the transaction completes in two BCLK periods. Each wait state adds one additional BCLK period. The following formula is used to calculate the total transfer time:

Total Transfer Time = N * (2+Tw) * (1 BCLK period)

As an example, a transfer of 64 doublewords (256 bytes) completes in 15.36 microseconds for a 32-bit transfer with a 8.33MHz BCLK, while a 16-bit transfer completes in 30.72 microseconds. This example assumes that no preempts occur during the transfer and the addressed slave is a zero wait state device.

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Chapter 7: EISA CPU and Bus Master Bus Cycles

Analysis of EISA Standard Bus Cycle

The timing diagram in figure 7-1 illustrates the timing for three bus cycles, the first of which has one wait state and the last two are zero wait state bus cycles. The numbered steps that follow correspond to the reference points in the illustration.

Tc Ts Tc Tc Ts Tc Ts Tc

BCLK

BE0#:BE3#

W/R#

START#

CMD#

NOWS#

LOCK#

Read

Data

8

Write

Data

Figure 7-1. The EISA Standard Bus Cycle

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EISA System Architecture

1.The first bus cycle after bus grant cannot use address pipelining. After the first bus cycle, however, the bus master can use address pipelining to output the address and M/IO# early.

2.After the bus master (or CPU) has requested and been granted the bus, the bus cycle begins on the rising edge of BCLK (the leading-edge of Ts) with the assertion of the START# signal by the current bus master. START# remains asserted for a full BCLK cycle (all of Ts). At the leading-edge of START#, the bus master or CPU places the address on the LA bus and byte enables and also outputs M/IO#. If address pipelining is active, the address, byte enables and M/IO# may be placed on the bus during the previous bus cycle. W/R# is set to the appropriate state at the beginning of the bus cycle.

3.If a write bus cycle is in progress, the bus master begins to drive the data onto the appropriate data paths at the midpoint of Ts.

4.The addressed EISA slave decodes the address and asserts either EX16# or EX32# indicating that it is an EISA device and the data size it's prepared to handle. I/O devices should also ensure that the AEN signal is deasserted before decoding an address. AEN is asserted by the DMA controller when it is placing a valid memory address on the address bus. In order to maintain ISA bus master compatibility, an EISA I/O slave should assert IO16# as well as EX16# or EX32#. EISA slaves that do not need to maintain ISA bus master compatibility do not need to assert IO16#. The system board develops M16# from EX16# or EX32# to maintain ISA bus master compatibility when communicating with ISA memory slaves. Note that EISA compressed mode is not supported in current implementations of EISA; however, if implemented the addressed slave should assert NOWS# prior to the end of Ts.

5.If the addressed slave must latch the address information, it should be latched on the trailing-edge of START#. The system board's data bus steering logic samples the EX16# and EX32# lines to determine if steering is necessary. CMD# is asserted by the system board coincidentally with the deassertion of START# by the bus master. Only the system board drives the CMD# line. CMD# then remains asserted until the end of the bus cycle. If support for EISA compressed bus cycles were implemented, the main CPU logic would sample NOWS# at the trailing-edge of start to determine if the addressed slave supports EISA compressed mode bus cycles.

6.EXRDY is sampled at the falling edge of every BCLK after CMD# is asserted. If sampled deasserted, the bus cycle is extended by one wait state (an additional Tc). Designers of EISA expansion cards are guaranteed that the address presented on the LA bus, the byte enable lines and the state of M/IO# will remain static until the midpoint of the first Tc period of the bus cycle.

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