Chapter 6: ISA Bus Cycles

ISA DMA Bus Cycles

ISA DMA Introduction

ISA machines use two Intel 8237 DMACs on the system board to implement the DMA logic. One of the DMACs is connected to the other in a master/slave configuration using channel zero on the master as the cascade input from the slave. Since each 8237 DMAC provides four DMA channels and one on the master is used as the cascade input from the slave, the ISA system provides a total of seven DMA channels. The four inputs to the slave DMAC are designated as channels zero – three, while the three inputs to the master are designated as channels five – seven.

In addition, the ISA machine implements the two DMACs in such a fashion that the three channels on the master (channels five – seven) are capable of performing 16-bit transfers, while the four channels on the slave (channels zero – three) are capable of performing 8-bit transfers.

Each DMA block data transfer can consist of up to 64K individual transfers. This limitation is imposed by the 16-bit transfer count register associated with each channel. This allows each of the channels to transfer up to 64KB of data. The 16-bit channels are also restricted to 64KB transfers because the DMA logic cannot increment the memory address across a 64K address boundary.

Each DMA channel can address any memory location within the 16MB range from 000000h to FFFFFFh. This limitation is imposed by the combination of the 16-bit memory address register associated with each channel in the DMAC and the 8-bit page register associated with each channel. This pair of registers associated with each channel provide a 24-bit memory address capability.

ISA expansion boards can become bus masters if they are connected to one of the three 16-bit DMA channels on the master DMAC (channels five – seven) and if the channel is programmed as a cascade channel. The ISA board may then request the use of the bus through the auspices of the master DMAC on the system board.

When a DMAC is bus master, it uses its own clock when executing bus cycles. This clock is referred to as the DMA clock and is 1/2 the BCLK frequency. Depending on the system design and the selected processor speed, this will yield a DMA clock of either 3MHz (6MHz AT), 4MHz (8MHz ISA-compatible machine), or 4.165MHz (8.33MHz ISA-compatible machine).

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EISA System Architecture

8237 DMAC Bus Cycle

The 8237 is built around a state machine with seven possible states, each one DMA clock period wide. Table 6-1 lists the clock period for the three possible processor speed settings.

Table 6-1. DMA Clock Speeds

Prior to receiving a DMA Request, the DMAC is in the idle state (Si). When a DREQ is sensed, the DMAC enters a state where it asserts HOLD (Hold Request) to the microprocessor and awaits the HLDA (Hold Acknowledge). This state is called SO (the letter O). The DMAC remains in the SO state until HLDA is sensed asserted.

The DMAC can then proceed with the DMA transfer. S1, S2, S3 and S4 are the states used to execute a transfer (of a byte or word) between the requesting I/O device and system memory. In addition, when accessing a device that is slow to respond, a DMA transfer cycle can be stretched by de-asserting the DMAC's READY input until the device is ready to complete the transfer. This causes the DMAC to insert wait states (Sw), in the bus cycle until READY is asserted again.

The actions described in table 6-2 take place during states S1 – S4.

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When compressed timing is selected, S3 is eliminated from the DMA transfer cycle. The only real purpose of S3 is to allow the read command line to be asserted for twice the duration that it is when compressed timing is active. Not all memory and I/O devices will tolerate this abbreviated read command duration, so it must be used cautiously.

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EISA System Architecture

When extended write is selected, it causes the write command line to be asserted during S3 rather than S4, effectively doubling the duration of the write command line's assertion period.

It should be obvious that extended write and compressed timing are mutually exclusive because S3 is essential for extended write and is eliminated when compressed timing is selected.

Table 6-3 illustrates the transfer speeds possible at the three clock speeds under the following conditions:

•Compressed timing turned off

•Compressed timing turned on

The table assumes that the transfer is no more than 256 bytes in length. This was assumed for simplicity's sake. Every 256 transfers the DMAC must insert an S1 state in the next bus cycle to update the middle byte of the memory address (A[15:8]), which must be latched into the external DMA address latch. This adds one DMA clock period to the duartion of every 257th bus cycle.

Table 6-3. ISA DMA Transfer Rates

When looking at table 6-3, keep in mind that each bus cycle consists of three DMA clock cycles with compressed timing turned off and two DMA clock cycles with compressed timing turned on.

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