CHAPTER 13

Time is of the Essence

Of crucial importance in many systems are time-related functions. This may manifest itself in the measurement of duration, event counting or control of an external physical event for known periods. An example of the former would be the time between pulses generated by the teeth on a flywheel to measure engine speed for a tachometer.

Where time is of the essence these functions are often best implemented by using hardware counters to time events. In this chapter we will look at the various timer modules which are available to the mid-range PIC family. After completion you should:

•Know how a Watchdog timer improves the robustness of a MCU-based system and how to use the integral PIC device.

•Be able to use the basic 8-bit Timer 0 module as both a counter and timer.

•Understand the function of the 16-bit Timer 1 module and its interaction with the Capture/Compare/PWM (CCP) modules.

•Be able to use the 8-bit Timer 2 module together with the CCP modules to generate a pulse-width modulated output.

Many MCU-based systems are hosted in an electrically hostile environment with noise induced outside both through logic lines and the power supply. Our example of an auto tachometer is typical of this situation, with induction from the high-voltage ignition sparks and alternator sourced ripple in the battery supply. No matter what precautions in shielding and filtering are taken, it is inevitable that on occasion the MCU will jump out of its proper location in Program memory and ‘run amok’ with potentially serious consequences on the controlled system.1 In some cases this is little more serious than requiring a manual reset.2 However, this is not possible in many situations; for example, in a pacemaker implanted in the patient’s body!

One solution to this problem is to use a counter/oscillator which resets the processor when it overflows. If the software is arranged to clear this counter on a regular basis so that overflow never occurs then the

1The same can happen due to software bugs.

2As in a Window’s PC.

362 The Quintessential PIC Microcontroller

MCU never resets. If something happens and the MCU jumps out of its normal loop then the counter will overflow and the MCU will be reset to its starting point. This counter circuit is given the name Watchdog timer.3

Fig. 13.1 The integral PIC Watchdog timer.

Rather than rely on external Watchdog timers, all PIC MCUs, even the early 12-bit PIC16C5XX family, have an integral module as illustrated in Fig. 13.1. A built-in oscillator separate from the processor clock runs continually if the Watchdog timer is enabled, with a nominal period of 18 ms. The integral capacitor/resistor timing network is not tightly specified and as a consequence the period will vary with device process, temperature and supply voltage from a minimum of 7 ms (lowest temperature −40◦C,

highest VDD 6 V) up to a maximum of 33 ms (highest temperature +85◦C, lowest VDD 2 V) – see Fig. 15.8 on page 448.

The Watchdog oscillator is followed by an 8-bit Watchdog postscaler counter. This prescaler be set to give Watchdog counter overflow timeout periods going up in powers of two up to nominally 18 × 128 ≈ 2.3 s

– 0.9 s minimum, 4.2 s maximum. The actual value is selected by the programmer using the PS[2:0] (Pre/Post Scaler rate Select) bits in the Option register (OPTION_REG) – see Fig. 13.2. The Watchdog postscaler and counter are both cleared with the clrwdt (CLeaR WatchDoG Timer) instruction and issuing this at regular intervals is the mechanism whereby the programmer prevents time-out.

3Other approaches typically are based on a retriggerable monostable.

364 The Quintessential PIC Microcontroller

Resetting initializes the Watchdog timer and zeros the postscaler so it’s not necessary to issue an extra clrwdt as we have done above. However, the initializing process will add to the time it takes to get into the normal main code and the normal loop clrwdt, thus an extra clrwdt at the end of any initializing code is useful insurance.

In the 12-bit PIC family the Watchdog time-out was the only way short of a Manual reset to awaken a device in the Sleep state. The sleep instruction resets the Watchdog and postscaler counters to give a full timeout period when entering the Sleep state. As the Watchdog oscillator is stand-alone it continues to run while the PIC is asleep. After the ordained period a Watchdog reset occurs and the PIC resumes execution with the instruction following sleep. If necessary the programmer can determine that the time-out occurred during the Sleep state by examining the TO bit.

The Watchdog awaken mechanism is not so important for the midand high-range PIC families. These can be awakened by an external interrupt, and where applicable the Timer 1 and Analog modules, both of which have the option of a self-standing clock oscillator. Where the watchdog is enabled and used in the Sleep mode the designer should be aware that the typical current consumption4 rises from typically 1.5 µA (24 µA maximum) to 10.5 µA (42 µA maximum). Where long-term battery operation is required (for example, see SAQ 12.6 on page 360) this presents serious problems. Running the processor continually at the lower frequency of 32.768 kHz with the Watchdog disabled takes typically 52 µA (105 µA maximum) in comparison.

The original 12-bit PIC16C5XX family features a basic 8-bit counter/- prescaler which was called a Real-Time Clock/Counter. Although this term was still used in the early 14-bit PIC16CXXX data sheets, the introduction of additional timers lead to the more consistent term Timer 0 (TMR0). However, the term RTCC is still to be found as a relic in older textbooks and software. For example, the CCS C compiler sets the Timer 0 clock source to external low-going edge with a prescale value of 4 by calling setup_counters(rtcc_ext_l_to_h, rtcc_div_4);.

From Fig. 13.3 we see that Timer 0 comprises a primary 8-bit counter located at File 1 in tandem with an optional 8-bit prescaler counter. This gives eight selectable clock rates into the primary counter as selected by the three PS[2:0] bits in OPTION_REG. This Timer 0 prescaler is actually

4The PIC16C74 with VDD = 4 V, −40◦C to +85◦C.

Fig. 13.3 Simplified equivalent circuit for Timer 0.

the same circuit as the Watchdog’s postscaler5 and PSA in OPTION_REG[3] must be set to 0 to assign the prescaler to Timer 0.

The prescaler is assigned to the Watchdog timer by default on Poweron/Manual reset and in this situation the primary counter is either clocked by the internal cycle clock Fosc at a rate XTAL/4 or from an outside source via the Timer 0 Clock Input RA4/T0CKI pin. The Timer 0 Clock Select

T0SC bit at OPTION_REG[5] is used to select the internal/external mode. When clocked from outside, the active edge is set using the Timer 0 Set Edge T0SE bit at OPTION_REG[4].

In order to synchronize the outside clock to the internal Timer 0 primary counter, a 2-stage shift register is used at the latter’s clock input.

This causes a 2 × Fosc/4 delay; 1 µs with an 8 MHz crystal. Where the primary counter is directly connected to the internal clock, this will cause

a 2-count delay before anything happens after a datum is written into Timer 0 at File 1. This synchronization is such that Timer 0 may be read from or written to in the normal way without interfering with any possible count action.

When the primary counter overflows (11111111 → 00000000) the Timer 0 Interrupt Flag T0IF is set. This event can be sensed by polling

INTCON[2] or if the Timer 0 Interrupt Enable mask bit T0IE in INTCON[5] is set an interrupt will automatically be generated – see Fig. 7.4 on page 178.

An external clock signal going directly into the primary counter should

be high for at least 2Tosc +20 ns and low for at least the same time. Thus for a 8 MHz crystal, Thigh should be 270 ns and the same for Tlow; a max-

5The PIC18CXXX family use separate scalers for the Watchdog timer and Timer 0.

366 The Quintessential PIC Microcontroller

imum frequency of 1.8 MHz. When the prescaler is used this minimum

total period of 4Tosc + 40 ns can be divided by the prescaler ratio. The input waveform is subject only to a minimum 10 ns pulse width. Thus

with a ÷256 setting, a nominally 50 MHz signal at T0CKI will be counted. When assigned to Timer 0 the prescaler is not readable, so the timer is not strictly a 16-bit counter. Reading Timer 0 does not a ect the prescaler but any instruction writing to it (eg. clrf 1, movwf 1) will both clear the

prescaler and the clock synchronizer.

As the prescaler is assigned to the Watchdog on Power on/Manual reset it can be subsequently changed over by clearing PSA. However, it is possible that this change-over could cause a Watchdog reset even if it is disabled. Microchip therefore recommend that the change-over be preceded by a clrwdt instruction; for example:

The code shows the prescaler divides clock input by four from the T0CKI pin, and incrementing on the \ . It is also possible to change the prescaler over from Timer 0 to the Watchdog timer ‘on the fly’. In the same manner the clrwdt should be executed before altering OPTION_REG to avoid a spurious Watchdog reset.

Timer 0 is mainly used either to count external events or to determine the period between external events. it can also be used to time software toggling port pins for precisely known durations, without tying up the processor in time-wasting delay routines.

Fig. 13.4 Counting cans of beans on a conveyer belt.

13. Time is of the Essence 369

The ISR itself is sandwiched between the normal context switching wrapper described in Program 7.2 on page 183. The core simply implements the following task list in no particular order:

•Toggle RB1 to signal the packing machine.

•Reset Timer 0 to −24.

•Increment the double-byte score count.

•Reset the Timer 0 Interrupt flag T0IE.

In Program 13.1 T0IE is tested on entry and if not set the ISR is exited. If there are other sources of interrupt then the switch would be to another part of the ISR, as shown in the listing on page 179.

For an alternative approach using hardware interrupts see Program 7.2 on page 183.

Our second example illustrates the use of Timer 0 as a clock to measure time between events. The events in question are R-points peaks in the ECG waveform illustrated in Fig. 7.1 on page 172. Here a peak detector interrupts the MCU, which keeps a 2-byte count from a 10 kHz external oscillator. In this manner the period between events can be determined on each event in increments of 100 µs, which we call here ji es. For our example we will modify the specification to eliminate this oscillator and use Timer 0 to keep a 1 ms 2-byte Ji y tally.

For this task we need to use the main PIC oscillator as the clock source together with the prescaler that so that Timer 0 overflows once per millisecond (103 µs). If we choose a 4.096 MHz crystal we have:

Time-out = 4.0964 × 256 × prescale ratio

which gives a required prescale ratio of 1:4.

With these requirements in mind we have for our initialization background software:

As well as enabling the Timer 0 interrupt, INTE is set to enable hardware interrupts from the INT pin which is going to signal an ECG peak. Neither

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Program 13.2 Measuring the ECG waveform period to a resolution of 1 ms.

; *************************************************************

;*************************************************************

;First save context in usual way

;*************************************************************

;The core code

; *************************************************************

the double-byte Ji y count nor Timer 0 need be cleared as the first reading of the series will always be erroneous – as the patient’s heartbeat is not synchronized to the PIC reset! However, file register NEW which is set to non zero each time an ECG peak is detected is cleared.

The core of the ISR shown in Program 13.2 implements the following task list when an interrupt is received:

1.IF Timer 0 interrupt.

• Increment 2-byte Ji y count.

13. Time is of the Essence 373

This needs to be done to allow Timer 1 to operate in the Sleep mode as Fosc is disabled in this situation. Apart from this case T1SYNC should be 0 as the lack of synchronization can lead to an unpredictable outcome if data is written into the two Timer 1 primary registers. If the Timer 1 state is to be updated, then the count should be stopped by clearing TMR1ON during this process; for instance:

Altering the state of Timer 1 will always clear the prescale counter. Timer 1 can be read at any time whatever the state of T1SYNCH. How-

ever, as only one byte can be read at a time6 it is possible that the timer may have overflowed from lower to higher byte in between the two reads; for example:

erroneously reads the state as 81FFh instead of 80FFh. This is even more likely to occur if another peripheral device interrupts between reads. A predictable reading can be obtained by either stopping Timer 1 before taking the readings or by reading the high byte first and then checking after the low byte has been read that the high byte has not changed.

The T1CON register is zeroed on Power-on and Manual reset – see Appendix B. This means that Timer 1 defaults to o with an internal clock source and prescale value of 1:1.

For our example assume that we have a low-power temperature logger that is to read the sensor and transmit its value back to base once every 15 minutes. It is proposed that Timer 1 be used to action this process and that the Timer 1 oscillator with a 32.768 kHz watch crystal is to give the timebase.

Timer 1 has a maximum overflow rate of 16 seconds, but if set to 4 seconds we will have a whole number of 15 interrupts per second. If we keep a Ji y count then a total of 15 × 15 = 225 will give 15 minutes. Thus our set up and main skeleton software would be something like that shown in Program 13.3. Here Timer 1 is set up to use the external

6In the PIC18CXXX family reading one of the bytes of Timer 1/3 automatically makes a copy of the other byte in a temporary register, e ectively giving a single 16-bit time sample.

13. Time is of the Essence 375

oscillator with a prescale ratio of 2:1, giving our 4 s ji y. In addition, both TMR1IE, PEIE and GIE mask bits are set to enable the interrupt on Timer 1 overflow.

The ISR simply adds one onto the Ji y count. This is tested for 225 in the background program after sleep and if equal it is zeroed, the temperature taken and transmitted to base.

Timer 1 can be reset to zero by any Compare/Compare/PWM CCP module. Some PIC devices have two CCP modules sharing the same timer, such as the PIC16C74, and in such cases the second module CCP2 is virtually identical to CCP1 and can share the same timer. With this in mind we will look just at CCP1 for convenience, pointing out any di erences at the relevant point. All CCP operations require Timer 1 to be configured in its synchronous mode; that is SYNCH = 0.

Each CCP module has an associated control register. For CCP1 this is CCP1CON at File 1Dh in which the lower four bits CCP1M[3:0] set the module mode. A setting of 0000, the reset value, disables the CCP module, resets the CCP output latch and clears the Capture mode prescaler. Modes 1000 – 1011 listed in Fig. 13.6 give four Compare modes. Here an equality comparator detects when the 16-bit Timer 1 datum equals the setting in the 16-bit CCPR1H:L (CCP Register 1) at File 15:16h respectively. When an equality match occurs the CCP1IF interrupt flag in PIR1[2] will be set and this can cause an interrupt if the corresponding CCP1IE mask bit in PIE1[2] is set.

Besides setting CCP1IF and depending on the setting of the CCP1M[3:0] mode bits, one of four actions are possible on Timer 1 matching CCPR1:

CCP Register 1

Fig. 13.6 The CCP1 module set to Compare mode.

376 The Quintessential PIC Microcontroller

1000:

Pin RC2/CCP1 is forced high.

1001:

Pin RC2/CCP1 is forced low.

1010:

Pin RC2/CCP1 unchanged, but CCP1IF still set.

1011:

Timer 1 is cleared and with CCP2 only7 an analog module conversion is initialized by setting GO/DONE – see Fig. 14.8 on page 404.

Where RC2/CPP1 or RC1/CCP2 are to be used as CCP outputs then the appropriate TRISC bit(s) should be cleared to set the pin direction to output. There is no way to directly reset or set the CCP latch other than zeroing the CCPCON register which resets the latch and disables the CCP module. In this case the state of the RC2/CCP1 pin will be that of PORTC[2] until the module is set to an appropriate mode, in which case the pin will reflect the state specified above when the match occurs.

As an example consider that we wish to set up Timer 1 as configured in the last example to generate an interrupt each 10 seconds. To do this we need set the timer to time-out after 16 s (prescale ratio 8:1) and then shorten the cycle. This is implemented by loading the CCPR1 register with the fraction 1016 −1, which translates to 9FFFh. Whenever Timer 1 reaches this value it will automatically be reset on the next clock input (that would have normally incremented the timer to A000h) and an interrupt will occur if the CCP1IE mask bit (and global PEIE and GIE masks) are set.

Initialization code for this is:

The PIC will then automatically be interrupted every ten seconds.

As CCP1 is not changed by Compare mode 1011 this pin can be used as a normal Port C input/output independently of the CCP1 module.

Where there are two CCP modules they can work in tandem using di erent modes, but the timebase will be common – see Example 13.3.

7This is the only functional di erence between CCP1 and CCP2.

13. Time is of the Essence 377

Modes 0100 – 0111 configure the appropriate CCP module to capture the state of Timer 1 when an ‘event’ occurs at the appropriate CCP pin. We can see from Fig. 13.7 that an event can be a falling or rising edge on the RC2/CCP1 pin or every 4th or 16th rising edge according to the CCP1M[3:0] mode bits. This Event prescaler is cleared when the mode bits are set to 0000.

Once a defined event has taken place the 16-bit state of Timer 1 is parallel loaded into the CCP register 1 and CCP1IF set. The processor can then subsequently read this frozen value – that is the time. If Timer 1 is reset after each capture then the sampled datum is the time since the last event. Alternatively, as Timer 1 continues to increment, its captured value can be subtracted from the previous reading to give the di erence. As the mode may be altered on the fly, the time between rising and falling edge on CCP1 can be measured by toggling CCP1M[0] between captures. This may cause the CCP1IF flag to be set. To prevent false interrupts, CCP1IE should be cleared before the change-over and CCP1IF after the change-over. Alternatively, the CCP1 module can be used to capture the rising edge and CCP2 the falling edge – see Example 13.3. There is no room for the CCP2IF and the associated interrupt mask CCP2IE mask bit in PIR1/PIE1. Instead bit 0 of PIR2/PIE2 are pressed into service and in many mid-range processors is the only occupant of these registers.

As our example, consider that we wish to measure the period of our ECG signal with the peak detector connected to pin CCP1. If we assume Timer 1 is clocked by its own 32.768 kHz watch crystal, our set up code is something like this:

Fig. 13.7 Capturing the time of an event.

13. Time is of the Essence 379

A more robust software system would also enable the Timer 1 overflow interrupt. if this occurs it indicates that the subsequent captured data will be invalid – although time-outs can be counted and thus extend the validity of the captured time. However, in our system it is more likely to be used to set o an alarm!

Timer 2 is an 8-bit counter which has both pre and postscalers. Unlike the two previous timers, output is not taken from the counter chain but from the Timer 2 Comparator. This compares the state of Timer 2 with that in the Period Register PR2. On equality an output pulse is generated which resets Timer 2 at the next clock pulse. This reset signal also sets the Timer 2 Interrupt Flag TMR2IF in PIR1[1]. The number of equality events to set TMR2IF and optionally create an interrupt, is a function of the postscaler. Any integer number between 1 and 16 events can be set up using the TOUTPS[3:0] (Timer 2 OUTput Post Scaler) in the Timer 2 CONtrol register at T2CON[5:2]. T2CON at File 12h also controls the prescaler, giving four divide ratios for the internal clock, and can also be used to disable the timer. The reset state of T2CON is all zeros, disabling the timer and giving a pre/post scaler ratio of 1:1.

The advantage of this architecture is that time-out can be fine tuned by setting the Period Register to an appropriate value, independently of a CCP module. The period until TMR2IF is set is given as:

4/Fosc × Prescale × (PR2 + 1) × Postscale

For our example, consider the need for an interrupt 100 times per second to scan a 7-segment display (see Program 11.8 on page 302) and that the main crystal is 4 MHz. Choosing a prescale ratio of 4:1 gives a clocking period for Timer 2 of 4 µs. If the Period Register is set to 249 then the Timer 2 comparator output period is 250 × 4 = 1 ms. Thus setting

Fig. 13.8 A simplified equivalent circuit for Timer 2.

380 The Quintessential PIC Microcontroller

the postscaler to 1:10 (1001) will give a 10 ms (100 Hz) interrupt rate. By varying the postscaler from 1 to 16 (TOUTPS[3:0] = 0000 to 1111) respectively we can have an interrupt rate from 1 to 16 ms. For fine adjustments a unit change in PR2 alters the rate by 4 × postscaler × µs.

Set up code for this example is:

One of the more common applications of MCU-based systems is the control of power circuits, such as heating, lighting and electric motor speed control. One approach to this problem would be to use a digital to analog converter, such as that discussed in Fig. 12.16 on page 328, driving a power amplifier. Linear control is expensive and ine cient due to the large current:voltage products that must be handled by the power amplifier. A rather more e cient and more cost e ective approach rapidly switches the load on and o at a reasonably fast rate. A power switch, such as a thyristor, dissipates relatively little power, as when the switch is o no current flows and when the switch is on the voltage across the switch is low – ideally zero.

An example of such a waveform is shown in Fig. 13.9. The average amplitude is simply A × N%, where N is the duty cycle percentage of the repeat period. If we vary N from 0 to 100% then the average power will vary in a like fashion – all without the benefit of analog circuitry. This digital to analog conversion technique is known as pulse width modulation (PWM).

The thermal or mechanical inertia of most high-power loads is such that even with a relatively low repetition rate (typically no lower than 100 Hz) the ‘bumps’ will be smoothed. Low switching rates are more efficient, as each switching action dissipates energy. If PWM is used for more conventional digital to analog conversion, such as for audio, then a

Fig. 13.9 Pulse width modulation.

13. Time is of the Essence 381

low-pass filter may be utilized to reduce the high-frequency harmonics. In such cases a sampling rate of at least ten times the maximum analog signal should be used to space out the harmonics (see Fig. 14.3 on page 396) and reduce the necessary filtering burden.

It is relatively easy to generate a PWM waveform solely in software by simply counting and setting a port pin when the count rolls over to zero and resetting the pin when it equals the datum representing the duty cycle. Thus if the duty cycle datum was 9Fh and the period count was module-256 (00–FFh) then the average power would be 62.5% (58 ).

CCP modules have a PWM mode in conjunction with Timer 2, as shown in Fig. 13.10. Here Timer 2 runs with a period determined by the main crystal, prescaler and Period Register 2 as previously described. When the Timer 2 comparator causes the count to reset, it also sets the PWM latch. This gives the PWM repeat period.

A second CCP equality comparator matches the 10-bit duty cycle number which is set up by the program in CCPR1L and the two bits DC1B[1:0] (Duty Cycle 1 Bits) in CCP1CON[5:4]. Taken together this gives a 10-bit duty-cycle datum DC1B[9:0]. This datum is loaded into the CCPR1H and a slave 2-bit latch each time Timer 2 rolls over. CCPR1H is not directly writable to in this mode. Thus we have the following sequence of operations repeated indefinitely:

Period Register

Fig. 13.10 Timer 2 and the PWM CCP mode.

382 The Quintessential PIC Microcontroller

1.Timer 2 increments.

2.When Timer 2:Prescaler equals DC1B[9:0] the PWM latch resets and pin CCP1 goes low.

ter/latch us updated. 4. Goto item 1.

From the above description we see that:

•The PWM period is set by the Timer 2/PR2 time-out.

•The duty cycle is set by the 10-bit datum in CCPR1L:CCP1CON[5:4].

•The duty cycle datum can be glitchlessly changed by the software at any time by updating the slave registers and will take e ect in the PWM period following this update.

•The RC2/CCP1 pin direction should be set to output.

Where the Timer 2 prescale is set to 1:1 the lower two bits used on the timer side are the quadrature clock phases described in Fig. 4.4 on page 87. This gives a period resolution equal to the crystal period. In all cases the datum in CCPR1L must be smaller than that in PR2, otherwise the PWM latch will never reset!

If PR2 is FFh then the resolution of the system is a full ten bits. Smaller values of Timer 2 period data will reduce this resolution. For example, if PR2 = 3Fh then the resolution is reduced to eight bits – six in PR2 and two in the prescaler.

For our example let us assume a crystal frequency of 20 MHz, a prescale ratio of 1:16 and a PR2 value of FFh. In this case the PWM frequency is 204 × 161 ×256 = 1.22 kHz. A prescale ratio of 1:1 would increase the period frequency to 19.53 kHz. Reducing the value in PR2 would also increase the repetition frequency. The programmer need only place the duty cycle datum in CCPR1L and CCP1CON[5:4] (the latter can be left at its reset value of zero if the datum is to be treated as 8-bit) and a PWM signal will automatically be generated with no software overhead. Set up code for this instance would be:

The Timer 2 postscaler does not a ect the PWM generation but still sets the TMR2IF in the normal way. The CCP1IF is not altered in this mode.

13. Time is of the Essence 383

If a second CCP module is used, an extra PWM output at pin RC1/CCP2 is available with a separate duty cycle but an identical period, as Timer 2 is a shared resource.

Examples

Example 13.1

Show how you could use Timer 0 to generate a PWM version of a digital byte in file register DATUM using pin RA0 as the output. Assuming an 8 MHz crystal, calculate the PWM duration.

Solution

Timer 0 will give a time-out related to a number loaded into the timer at the beginning of the period. If we load in the the 2’s complement of the byte (the negative value) then the duration will be proportional to this value – the larger it is the longer the timer has to count before overflowing. Conversely loading in the value of DATUM will give a time-out duration inversely proportional to the value. By alternately loading the 2’s complement of DATUM and making the pin high followed by DATUM itself making the pin low will give us a total period approximately the same as a total Timer 0 time-out as if counting through all 256 states.

The coding of Program 13.5 sets up Timer 0 to count 2 MHz internal clock cycles with no prescale. Thus the total PWM rate is 2562 or 7.8125 KHz. When Timer 0 overflows it generates an interrupt. The ISR checks the state of PORTAA[0] and if 0 changes its state and then calculates the 2’s complement of the data byte (invert plus one). However, there is a 2-cycle delay in Timer 0 responding when its state is changed due to the clock synchronizer circuit and so another two is added to compensate for this extra delay. If the port pin was already 1 then it is zeroed and the datum itself plus the compensatory two is written into Timer 0.

Adding the compensation will cause problems at either extremes of the mark:space ratio. Why is this so and what action could you take to ameliorate it?

Example 13.2

A certain tachometer is to register engine speed in the range 0–12,000 rpm (revolutions per second). The engine generates one pulse per revolution and it is intended that a PIC16C74 be used to count the number of pulses each second and calculate the equivalent rpm. Using two of the three available timers can you design a suitable hardware-software configuration?

Solution

13. Time is of the Essence 387

CCP1

CCP2

Fig. 13.11 An event manifesting itself as a pulse duration.

then we have as our counting rate 500 kHz; i.e. the system resolution is 2 µs. The overall maximum duration that can be measured in this way is 216 × 2 = 131, 077µs which is large enough not to overflow.

The ISR in Program 13.7 simply tests each CCP interrupt flag in turn and goes to the appropriate routine. If CCP1 has signalled a / event

then the timer is zeroed to restart the count. Timer 1 has been configured to increment at a 500 kHz rate and when the next \ occurs the CCP2 module captures the state of this timebase and places it in the 16-bit CCPR2 register. The ISR then copies it into the two file registers TIME:TIME+1 and this is the period in 2 µs ticks.

Actually resetting Timer 1 on the first event introduces some inaccuracy into the process as the clearing event takes some time. In our application this is of little consequence but it may cause some problems in shorter high-resolution situations. In this case Timer 1 can be left to run continually and the two captured 16-bit data subtracted to give the required di erence at relative leisure.

Self-assessment questions

13.1Using Timer 1 and CCP1, design a system to generate a continuous square wave with a total period of 20 ms from RC2/CCP1. You may assume that the main crystal is 8 MHz. Hint: Remember that the state of the CCP pin will only change when a match occurs so the Compare mode will have to be changed on the fly each 10 ms.

13.2The echo sounding hardware shown in Fig. 7.6 on page 195 uses an external 1.72 kHz oscillator to interrupt the PIC once per 5.813 ms, that is once every time sound travels 1 cm through air. Assuming that a 20 MHz PIC is used, show how Timer 2 could be used to generate this interrupt rate to an accuracy better than 0.1%.

13.3The PIC family has only one hardware input, namely INT/RB0. Suggest

some way to use Timer 0 to simulate another hardware interrupt with pin T0CKI/RA4.