Programmer’s Model for Test
4.3.4Test output register 2, SCIITOP2
SCIITOP2 is the integration test output register 2. In integration test mode, the primary and intra-chip outputs can be controlled by writes to the SCIITOP2 register. Reads of the intra-chip bits return the value present at the output of the test multiplexor. Reads of the primary output bits return the value written into the respective SCIITOP2 register bit. Table 4-5 shows the bit assignment of the SCIITOP2 register.
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Table 4-5 SCIITOP2 register bits |
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Bits |
Name |
Description |
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15:13 |
- |
Reserved, unpredictable when read. |
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12 |
SCIINTR |
Intra-chip output. Writes specify the value to be driven on |
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the SCIINTR line in the integration test mode. |
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Reads return the value of SCIINTR at the output of the |
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test multiplexor. |
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11 |
SCICLKACTINTR |
Intra-chip output. Writes specify the value to be driven on |
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the SCICLKACTINTR line in the integration test mode. |
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Reads return the value of SCICLKACTINTR at the |
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output of the test multiplexor. |
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10 |
SCICLKSTPINTR |
Intra-chip output. Writes specify the value to be driven on |
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the SCICLKSTPINTR line in the integration test mode. |
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Reads return the value of SCICLKSTPINTR at the |
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output of the test multiplexor. |
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9 |
SCIRORINTR |
Intra-chip output. Writes specify the value to be driven on |
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the SCIRORINTR line in the integration test mode. |
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Reads return the value of SCIRORINTR at the output of |
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the test multiplexor. |
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8 |
SCICLKOUT |
Primary output. Writes specify the value to be driven on |
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the SCICLKOUT line in the integration test mode. Reads |
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return the value written into the SCIITOP2 SCICLKOUT |
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register bit. |
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7 |
nSCICLKOUTEN |
Primary output. Writes specify the value to be driven on |
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the nSCICLKOUTEN line in the integration test mode. |
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Reads return the value written into the SCIITOP2 |
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nSCICLKOUTEN register bit. |
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6 |
nSCICLKEN |
Primary output. Writes specify the value to be driven on |
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the nSCICLKEN line in the integration test mode. Reads |
return the value written into the SCIITOP2 nSCICLKEN register bit.
4-8 |
Copyright © 2001 ARM Limited. All rights reserved. |
ARM DDI 0228A |
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Programmer’s Model for Test |
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Table 4-5 SCIITOP2 register bits (continued) |
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Bits |
Name |
Description |
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5 |
nSCIDATAOUTEN |
Primary output. Writes specify the value to be driven on |
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the nSCIDATAOUTEN line in the integration test mode. |
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Reads return the value written into the SCIITOP2 |
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nSCIDATAOUTEN register bit. |
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4 |
nSCIDATAEN |
Primary output. Writes specify the value to be driven on |
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the nSCIDATAEN line in the integration test mode. Reads |
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return the value written into the SCIITOP2 nSCIDATAEN |
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register bit. |
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3 |
SCIVCCEN |
Primary output. Writes specify the value to be driven on |
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the SCIVCCEN line in the integration test mode. Reads |
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return the value written into the SCIITOP2 SCIVCCEN |
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register bit. |
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2 |
SCIFCB |
Primary output. Writes specify the value to be driven on |
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the SCIFCB line in the integration test mode. Reads return |
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the value written into the SCIITOP2 SCIFCB register bit. |
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1 |
nSCICARDRST |
Primary output. Writes specify the value to be driven on |
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the nSCICARDRST line in the integration test mode. |
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Reads return the value written into the SCIITOP2 |
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nSCICARDRST register bit. |
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0 |
SCIDEACACK |
Primary output. Writes specify the value to be driven on |
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the SCIDEACACK line in the integration test mode. |
Reads return the value written into the SCIITOP2
SCIDEACACK register bit.
4.3.5Test data register, SCITDR
SCITDR enables data to be written into the receive FIFO and read out from the transmit FIFO for test purposes. This test function is enabled by the TESTFIFO signal, bit 1 of the test control register (SCITCR). Table 4-6 shows the bit assignment of the SCITDR register.
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Table 4-6 SCITDR register bits |
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Bits |
Name |
Description |
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15:0 |
DATA |
When the TESTFIFO signal is asserted, data can be written into the |
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receive FIFO and read out of the transmit FIFO. |
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ARM DDI 0228A |
Copyright © 2001 ARM Limited. All rights reserved. |
4-9 |