Virtuoso XL Layout Editor User Guide

Using Spice and CDL For Netlist Driven Layout Generation

C

Using Spice and CDL For Netlist Driven

Layout Generation

Introduction

The VXL Spice reader will read two styles of Spice, those being generic SPICE3 (Hspice like) and CDL. Within these styles, only those constructs needed to support the netlist input requirements of VXL will be read.

Specifying Spice Designs

A Spice design is specified to VXL via a single Spice netlist file. The cell defined at the file level (ie : outside of any .SUBCKT block) is designated as the top level cell and is assigned the name *TOP-CELL-(last part of file name). For example, for the Spice file/mycds/ mydir/des_a.sp, the top level cell is assigned the name *TOP-CELL-des_a. All other cells specified in the design must be defined using the.SUBCKT or .MODEL statements. Some additional cells may be created via an automatic mechanism as needed by the Spice reader.

The Spice netlist file can include other Spice netlists by using the.INCLUDE statement. All cells defined within included files must be defined using the.SUBCKT or .MODEL statements. Further, all cell names in the design must be unique. The spice style (SPICE3 or CDL) must be specified to VXL.

Cell Creation Rules

Cells associated with a SUBCKT instance must be created using a .SUBCKT statement.

Cells associated with a mosfet, jfet, mesfet, BJT (bipolar), or diode instance can be created one of 3 ways

1.By a .SUBCKT statement in which case the specified ports are used.

2.By a .MODEL statement :

Virtuoso XL Layout Editor User Guide

Using Spice and CDL For Netlist Driven Layout Generation

a.Type nmos or pmos for a mosfet, in which case the ports D,G,S,B are used

b.Type njf or pjf for a jfet, in which case the ports D,G,S are used

c.Type nmf or pmf for a mesfet, in which case the ports D,G,S are used

d.Type npn or pnp for a BJT device, in which case the ports C,B,E are used

e.Type d for a diode, in which case the ports PLUS,MINUS are used

3.Automatically, by being an unresolved reference of a mosfet, jfet, mesfet, BJT, or diode instance in which case the ports D,G,S,B , D,G,S , D,G,S , C,B,D , or PLUS,MINUS respectively are used.

Cells associated with a capacitor or resistor can be created in one of four ways

1.By a .SUBCKT statement in which case the specified ports are used.

2.By a .MODEL statement :

a.Type c for a capacitor, in which case the ports PLUS,MINUS are used

b.Type r for a resistor, in which case the ports PLUS,MINUS are used

3.Automatically, by being an unresolved reference of a capacitor or resistor instance, in which case the ports PLUS,MINUS are used.

4.Automatically, for cases where no model is specified, in which case the cell "-RES-" is created for a resistor and "-CAP-" is created for a capacitor. In both cases, the ports PLUS,MINUS are used.

Inductor references do not allow specification of a model. However, a default cell-IND- is created for all inductors. The ports PLUS,MINUS are used.

Voltage Source references do not allow specification of a model. However, a default cell named -VOLT- is created for all voltage sources. The ports PLUS, MINUS are used.

Note: The implications of the above are that references to mosfet, jfet, mesfet, BJT, capacitor, resistor, and diode models may be assumed but references to subckt cells are never assumed.

Virtuoso XL Layout Editor User Guide

Using Spice and CDL For Netlist Driven Layout Generation

Character Considerations

Character Case

In general case sensitivity will be recognized, however the following rules and exceptions will apply

1.All keywords will be treated as case insensitive.

2.The Scale parameter on the .OPTION line will be treated as case insensitive.

3.On fet references, if implied width and length values are specified, uppercaseW and L will be the assigned parameters.

The * Character

Spice

The * at the beginning of a column denotes the beginning of a comment which ends at the end of line. The * PORT statement is treated as a valid statement to determine port direction.

CDL

The * at the beginning of a column denotes the beginning of a comment which ends at the end of line. If this occurs before a command, then the command should be read by Dracula but not by the circuit simulator. For parsing CDL, the keywords .GLOBAL, .INCLUDE,

.OPTION, and .PARAM will be processed even if a * precedes them.

The $ Character

Spice

Under most circumstances the $ denotes the beginning of a comment which ends at the end of line. The exceptions are when the $ is part (but not the start) of a name or when it is part of a quoted string. In these cases $ is treated as any other character.

Virtuoso XL Layout Editor User Guide

Using Spice and CDL For Netlist Driven Layout Generation

CDL

The $ before a non-command field denotes that the following field should be read by Dracula but not circuit simulator. The $ before a command indicates that the line should be treated as a comment. For parsing CDL, any $ before a name field will be ignored.

Characters in Names

Spice

A name may start with an alpha character or the following 3 characters % _ | . The allowable characters following the first character are alphanumeric, or the following seventeen

CDL

A name may start with an alpha character or the following four characters % _ | $ . The allowable characters following the first character are alphanumeric, or the following twenty

Pin, Terminal, and Net Names

Pins, terminals, and nets are given additional naming latitude. In addition to the names allowed by the general naming requirements under the Spice and CDL sections, pin, terminal, and net names are allowed to be a non-negative integer or a pair of non-negative integers separated by a colon. Examples of such allowable names are 0, 17, and 4:2 . Further, net

0 is always treated as a global ground net.

Spice Statements

Conventions for Format Descriptions

{ } surround optional elements in a description of a syntax

| denotes OR

… denotes a list

numval represents a value which must be numeric (4, -2.2, 3.75U, -3.56e-7)