- •Introduction
- •Outline
- •PWB Construction
- •PWB/CCA Examples
- •Types of Rigid PWB
- •Types of Flex PWB
- •Footnotes on Flex PWBs
- •PWB Stack-Ups (1 and 2 Layer)
- •Multi-Layer PWBs
- •Exploded View of Multi-Layer PWB
- •Multi-Layer Stack-Up Examples
- •PWB Stack-Up Guidelines
- •PWB Materials
- •PWB Materials
- •PWB Material Examples
- •Dielectric, Common Thickness
- •Copper Options
- •Etch-Back
- •Etch-Back
- •Signal Distribution
- •Single Ended Structure Examples
- •Differential Structure Examples
- •PWB traces as Transmission Lines
- •Characteristic Impedance
- •Trace Impedance
- •Strip-Line & Micro-Strip Impedance
- •Asymmetrical Strip-Line Impedance
- •Impedance Examples
- •Loss
- •Conductor Loss
- •Loss due to Skin Effect & Roughness
- •Time Delay
- •Signal Dispersion
- •Signal Dispersion
- •Signal Dispersion Example
- •Mitigation of Dispersion
- •Coupling
- •Coupling Examples
- •Mitigation of Coupling
- •Differential Pairs
- •Differential Pair Routing Options
- •Differential Impedance Definitions
- •Differential Impedance Examples
- •Field Intensity - 1
- •Field Intensity – 2
- •Field Intensity - 3
- •Field Intensity - 4
- •PWB Pad and Trace Parameters
- •Vias
- •Fine Pitch BGA (FG456) Package
- •Fine Pitch BGA (FG1156) Package
- •Via Parameters
- •Source Terminations
- •Destination Terminations
- •“Intentional” Mismatch Example
- •“Intentional” Mismatch Example
- •Power Distribution Purpose
- •Supply Power Loss Budget
- •DC Loss Model
- •Power Distribution Considerations
- •Plane Capacitance, Inductance, Resistance
- •Capacitor Parameters
- •Capacitor Parameters
- •Capacitor Guidelines
- •Capacitor Mounting Pads
- •Decoupling Examples
- •Trace Width Example
- •References
- •References (continued)
- •Material Suppliers
- •PWB Fabricators
- •Design Tools
Capacitor Mounting Pads
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0.9 nH |
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0.6 nH |
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0.5 nH |
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0.4 nH |
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Note:
Most PWB processes do not allow via-in-pad geometries
7.2 nH/in for 20 mil trace in addition to via and pad inductance
Improving Geometries
Notes:
1.Copper: 1 oz, electrodeposited, strip-line
2.FR4 dielectric constant: 4.50, loss tangent 0.025, height 10 mils
Revision 4 |
Copyright Telephonics 2002-2005 |
71 |
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Decoupling Examples
♦ 100 MHz Logic Device, 100 mA to 150 mA step load change
6.8 uF, Ripple: 1 Vpp |
6.8 uF + 0.1 uF, Ripple: 0.3 Vpp |
6.8 uF + 0.1 uF + 0.01 uF, |
6.8 uF + 0.1 uF + 0.01 uF w/ long |
Ripple: 0.1 Vpp |
traces, Ripple: 1.1 Vpp |
Revision 4 |
Copyright Telephonics 2002-2005 |
72 |
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Current Carrying Capability of PWBPWB
Traces
♦Trace Cross section (w,t)
♦Position of trace (outer layer, inner layer)
♦Maximum acceptable temperature rise
♦IPC-2221, Figure 6-4, can be used as general guideline
♦Thermal modeling may be needed in critical applications
Revision 4 |
Copyright Telephonics 2002-2005 |
73 |
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Trace Width Example
♦Application
-Inner trace, 1 ounce, maximum fault current is 2 Amps
-Max CCA temp +90 °C, max PWB temp +150 °C, Margin 30 °C
-Allowable Temp rise = 150 – 90 – 30 = 30 °C
♦Determine Cross Section from “C” is 56 sq mils
♦Determine width from “B” to be 40 mils
Revision 4 |
Copyright Telephonics 2002-2005 |
74 |
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References
and
Vendors
Revision 4 |
Copyright Telephonics 2002-2005 |
75 |
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