Overview

The ARM7TDMI-ICEBreaker module, hereafter referred to simply as ICEBreaker, provides integrated on-chip debug support for the ARM7TDMI core.

ICEBreaker is programmed in a serial fashion using the ARM7TDMI TAP controller. It consists of two real-time watchpoint units, together with a control and status register. One or both of the watchpoint units can be programmed to halt the execution of instructions by the ARM7TDMI core via its BREAKPT signal. Execution is halted when a match occurs between the values programmed into ICEBreaker and the values currently appearing on the address bus, data bus and various control signals. Any bit can be masked so that its value does not affect the comparison.

Figure 83 shows the relationship between the core, ICEBreaker and the TAP controller. Either watchpoint unit can be configured to be a watchpoint (monitoring data accesses) or a breakpoint (monitoring instruction fetches). Watchpoints and breakpoints can be made to be datadependent.

Two independent registers, Debug Control and Debug Status, provide overall control of ICEBreaker’s operation.

Note: Only those signals that are pertinent to ICEBreaker are shown.

Figure 83. ARM7TDMI Block Diagram

DBGRQI

A[31:0]

D[31:0]

nOPC

nRW

TBIT

MAS[1:0]

Processor ICEBreaker

nTRANS

DBGACKI

BREAKPTI

IFEN

ECLK

nMREQ

SDIN SDOUT

nTRST

TAP

EXTERN1

EXTERN0

RANGEOUT0

RANGEOUT1

DBGACK

BREAKPT

DBGRQ

DBGEN

TCK

TMS

TDI

TDO