Example system: The ARM7TDMI Testchip

Connecting ARM7TDMI’s data bus, D[31:0] to an external shared bus requires some simple additional logic. This will vary from application to application. As an example, the following describes how the ARM7TDMI macrocell was connected to the bi-directional data bus pads of the ARM7TDMI testchip.

In this application, care must be taken to prevent bus clash on D[31:0] when the data bus drive changes direction. The timing of nENIN, and the pad control signals must be arranged so that when the core starts to drive out, the pad drive onto D[31:0] switches off before the core starts to

Figure 73. The ARM7TDMI Testchip Data Bus Circuit

drive. Similarly, when the bus switches back to input, the core must stop driving before the pad switches on.

All this can be achieved using a simple non-overlapping clock generator. The actual circuit implemented in the ARM7TDMI testchip is shown in Figure 73. Note that at the core level, TBE and DBE are tied HIGH (inactive). This is because in a packaged part, there is no need to ever manually force the internal buses into a high impedance state. Note also that at the pad level, the signal EDBE is factored into the bus control logic. This allows the external memory controller to arbitrate the bus and asynchronously disable ARM7TDMI testchip if required.

ARM7TDMI

Core

Figure 74 shows how the various control signals interact. Under normal conditions, when the data bus is configured as i np u t, n E N O U T i s HIG H, n E N 1 i s L O W , a nd nEN2/nENIN is HIGH. Thus the pads drive XD[31:0] onto

D[31:0].

When a write cycle occurs, nRW is driven HIGH to indicate a write during phase 2 of the previous cycle, (ie, with the address). During phase 1 of the actual cycle, nENOUT is driven LOW to indicate that ARM7TDMI is about to drive

the bus. The falling edge of this signal makes nEN1 go HIGH, which disables the input half pad from driving D[31:0]. This in turn makes nEN2 go LOW, which enables the output half of the pad so that the ARM7TDMI is now driving the external data bus, XD[31:0]. nEN2 is then buffered and driven back into the core on nENIN, so that finally the ARM7TDMI macrocell drives D[31:0]. The delay between all the signals ensures that there is no clash on the data bus as it changes direction from input to output.

Figure 74. Data Bus Control Signal Timing

nENOUT

nEN1

nEN2/ nENIN

D[31:1]

When the bus turns around to the other direction at the end of the cycle, the various control signals switch the other way. Again, the non-overlap ensures that there is never a bus clash. This time, nENOUT is driven HIGH to denote that ARM7TDMI no longer needs to drive the bus and the core’s output is immediately switched off. This causes nEN2 to disable the output half of the pad which in turn

causes nEN1 to switch on the input half. Thus, the bus is back to its original input configuration.

Note that the data out time of ARM7TDMI is not directly determined by nENOUT and nENIN, and so delaying exactly when the bus is driven will not affect the propagation delay. Please refer to Timing Diagrams on page 189 for timing details.