Architecture
ARM7TDMI Block Diagram
Figure 1. ARM7TDMI Block Diagram
RANGEOUT0 
RANGEOUT1 
EXTERN1 
EXTERN0 
nOPC nRW MAS[1:0]
nTRANS nMREQ
A[31:0]
D[31:0]
DIN[31:0]
DOUT[31:0]
ICEBreaker
Bus Splitter
Scan Chain 2 |
Scan Chain 0 |
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Core |
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Other |
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Signals |
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Scan Chain 1 |
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TAP controller
TCK TMS nTRST TDI TDO TAPSM[3:0] IR[3:0] SCREG[3:0]
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ARM7TDMI Core Diagram
Figure 2. ARM7TDMI Core
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A[31:0] |
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ALE |
ABE |
I |
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n |
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Scan |
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c |
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Control |
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r |
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Address Register |
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e |
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P |
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m |
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e |
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C |
Address |
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t |
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b |
Incrementer |
e |
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r |
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u |
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b |
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Register Bank |
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s |
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(31 x 32-bit registers) |
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A |
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(6 status registers) |
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L |
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U |
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b |
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B |
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u |
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s |
A |
32 x 8 |
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b |
Instruction |
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Multiplier |
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Decoder |
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u |
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b |
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& |
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s |
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Control |
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u |
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Logic |
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s |
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Barrel |
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Shifter |
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32-bit ALU |
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Write Data Register |
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Instruction Pipeline |
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& Read Data Register |
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& Thumb Instruction Decoder |
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nENOUT nENIN
DBE |
D[31:0] |
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DBGRQI
BREAKPTI
DBGACK
ECLK
nEXEC
ISYNC
BL[3:0]
APE
MCLK
nWAIT
nRW
MAS[1:0]
nIRQ
nFIQ
nRESET
ABORT
nTRANS
nMREQ
nOPC
SEQ
LOCK
nCPI
CPA
CPB
nM[4:0]
TBE
TBIT 
HIGHZ
4 |
Architecture |
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ARM7TDMI Functional Diagram
Figure 3. ARM7TDMI Functional Diagram
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MCLK |
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Clocks |
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nWAIT |
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ECLK |
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nIRQ |
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Interrupts |
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nFIQ |
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ISYNC |
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nRESET |
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BUSEN |
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HIGHZ |
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BIGEND |
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nENIN |
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Bus |
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nENOUT |
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nENOUTI |
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Controls |
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ABE |
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APE |
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ALE |
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DBE APE |
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TBE |
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BUSDIS |
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ECAPCLK |
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Power |
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VDD |
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VSS |
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DBGRQ |
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BREAKPT |
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DBGACK |
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nEXEC |
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Debug |
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EXTERN 1 |
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EXTERN 0 |
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DBGEN |
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RANGEOUT0 |
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RANGEOUT1 |
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DBGRQI |
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COMMRX |
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COMMTX |
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Architecture
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TCK |
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TMS |
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TDI |
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nTRST |
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TDO |
Boundary |
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TAPSM[3:0] |
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IR[3:0] |
Scan |
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nTDOEN |
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TCK1 |
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TCK2 |
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SCREG[3:0] |
Boundary Scan |
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11 |
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Control Signals |
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nM[4:0] |
Processor |
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Mode |
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ARM7TDMI |
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TBIT |
Processor |
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State |
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A[31:0] |
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DOUT[31:0] |
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Memory |
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D[31:0] |
Interface |
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DIN[31:0] |
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nMREQ |
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SEQ |
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nRW |
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MAS[1:0] |
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BL[3:0] |
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LOCK |
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nTRANS |
Memory |
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ABORT |
Management |
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nOPC |
Interface |
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nCPI |
Coprocessor |
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CPA |
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Interface |
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CPB |
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5
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Architecture |
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