Index

A

B

C

Access sequencing 2-9

Bank burst read delay control register

Clock

Address mapping

3-12

feedback 2-48

external memory banks

2-9

Bank control register 3-12

frequency selection 2-7

memory bank registers

2-9

Bank idle control register 3-9

single output 2-51

AHB

Bank output enable assertion delay

Connections 1-6

slave interface connections 2-53

control register 3-11

Core block diagram 2-4

AMBA

1-3

Bank read wait state register 3-10

AHB

2-8

Bank status register 3-16

D

AHB interface

2-4

Bank write enable assertion delay

compatibility

1-2

control register

3-11

typical microcontroller system

1-4

Bank write wait state register

3-10

Data bus interface 2-3

typical microcontroller system with

Big-endian 2-43

Data bus steering

SDRAM controller 1-5

read for 16-bit external bus

2-47

little and big-endian

2-43

Asynchronous

read for 32-bit external bus

2-47

Design considerations

2-39

burst and page mode devices

2-16

read for 8-bit external bus

2-46

external wait control 2-33

Booting from ROM after reset

2-54

E

memory device accesses 2-11

Bus turnaround 2-30

static memory read control

2-11

Byte lane control

static memory write control

2-23

little and big-endian

2-43

EBI 2-5

Byte lane write control

2-39

use 2-58

Endian support 2-2

ARM DDI 0236A

Copyright © 2001. All rights reserved.

Index-1

External bank SMCS7 size

P

SMBCRx example 3-16

configuration 2-55

SMBCR0-7 3-12

External bus interface 2-5

Pad interface

2-3, 2-5, 2-48

SMBIDCYR0-7 3-9

External memory banks

Peripheral ID0 register

3-19

SMBSR0-7 3-16

address mapping 2-9

Peripheral ID0-3 register 3-18

SMBWSTBRD0-7 3-12

Peripheral ID1 register

3-20

SMBWSTOEN0-7 3-11

F

Peripheral ID2 register

3-20

SMBWSTRD0-7 3-10

Peripheral ID3 register

3-20

SMBWSTWEN0-7 3-11

PrimeCell AHB SMC

SMBWSTWRR0-7 3-10

Flash memory

2-28

features 1-2

SSMC control 3-18

Floating bytes

PrimeCell ID0 register

3-21

SSMC status

3-17

elimination

2-43

PrimeCell ID0-3 register 3-21

SSMC test control 4-3

PrimeCell ID1 register

3-22

SSMC test input

4-3

L

PrimeCell ID2 register

3-22

SSMC test output

4-4

PrimeCell ID3 register

3-22

SSMCCR

3-18

PrimeCell SMC

SSMCITCR

4-3

Little-endian 2-43

block diagram

2-2

SSMCITIP

4-3

read for 16-bit external bus

2-45

I/O connections

1-5

SSMCITOP

4-4

read for 32-bit external bus

2-45

memory banks

2-2

SSMCPCellID0

3-21

read for 8-bit external bus

2-44

overview

2-2

SSMCPCellID0-3 3-21

PrimeCell SSMC

SSMCPCellID1

3-22

M

operation

2-7

SSMCPCellID2

3-22

registers

3-3

SSMCPCellID3

3-22

Programmer’s model 3-2

SSMCPeriphID0

3-19

Memory

SSMCPeriphID0-3 3-18

bank select

2-8

R

SSMCPeriphID1

3-20

shadowing

2-54

SSMCPeriphID2

3-20

supported 1-7

SSMCPeriphID3

3-20

width 2-9

Registers

SSMCSR

3-17

16-bit device interconnection

2-50

bank burst read delay control 3-12

summary

3-3

32-bit device interconnection

2-50

bank control 3-12

test 4-3

8-bit device interconnection

2-49

bank idle control 3-9

ROM

Memory bank registers

bank output enable assertion delay

booting after reset 2-54

address mapping 2-9

control

3-11

Memory banks

bank read wait state

3-10

S

access 2-39, 2-41

bank status 3-16

bank write enable assertion delay

N

control

3-11

Signals

bank write wait state

3-10

AMBA AHB interface

A-2

A-5

Peripheral ID0

3-19

AMBA AHB master interface

Non-AMBA AHB signals A-7

Peripheral ID0-3 3-18

AMBA AHB slave interface

A-3

Peripheral ID1

3-20

Internal A-7

O

Peripheral ID2

3-20

Single output clock

2-51

Peripheral ID3

3-20

Slave interface connections

2-53

PrimeCell ID0

3-21

SMBCR0-7 register

3-12

Output

PrimeCell ID0-3 3-21

SMBIDCYR0-7 register 3-9

single clock

2-51

PrimeCell ID1

3-22

SMBSR0-7 register

3-16

Output enable programmable delay

PrimeCell ID2

3-22

SMBWSTBRD0-7 register

3-12

2-11

PrimeCell ID3

3-22

SMBWSTOEN0-7 register

3-11

Index-2

Copyright © 2001. All rights reserved.

ARM DDI 0236A

ARM DDI 0236A

Copyright © 2001. All rights reserved.

Index-3

Index-4

Copyright © 2001. All rights reserved.

ARM DDI 0236A